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    Microchip Technology Inc MPT-36C

    TVS DIODE 36VWM 54.3VC DO13
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    Microchip Technology Inc MPT-36C 21 Weeks
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    NAC MPT-36C 14
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    Microchip Technology Inc MPT-36C-TR

    BI-DIRECTIONAL TVS
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    Microchip Technology Inc MPT-36C/TR

    ESD Protection Diodes / TVS Diodes Bi-Directional TVS
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    NAC MPT-36C/TR 14
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    PT36C Datasheets (9)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    PT36CB010 Kappa Technologies 3-BIT PROGRAMMABLE DELAY LINE Scan PDF
    PT36CB020 Kappa Technologies 3-BIT PROGRAMMABLE DELAY LINE Scan PDF
    PT36CB030 Kappa Technologies 3-BIT PROGRAMMABLE DELAY LINE Scan PDF
    PT36CB050 Kappa Technologies 3-BIT PROGRAMMABLE DELAY LINE Scan PDF
    PT36CB100 Kappa Technologies 3-BIT PROGRAMMABLE DELAY LINE Scan PDF
    PT36CB150 Kappa Technologies 3-BIT PROGRAMMABLE DELAY LINE Scan PDF
    PT36CB200 Kappa Technologies 3-BIT PROGRAMMABLE DELAY LINE Scan PDF
    PT36CB400 Kappa Technologies 3-BIT PROGRAMMABLE DELAY LINE Scan PDF
    PT36CB500 Kappa Technologies 3-BIT PROGRAMMABLE DELAY LINE Scan PDF

    PT36C Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    transistor pt36c

    Abstract: gp714 diode GP113 transistor pt42c diode gp116 GP114 GP021 PT36c gp627 GP111
    Text: OR4E FPGA Ver 2.0 1 4/1/2002 Lattice Semiconductor Corp Series 4 FPGA Evaluation Board Diagram Revision 2.0 OR4E FPGA Ver 2.0 2 4/1/2002 Lattice Semiconductor Corp JTAG Programming Connection J55 Schematic page 4 An 8-pin connection to the JTAG interface used for programming.


    Original     		PDF ADDR17 ADDR16 DATA31 DATA30 DATA29 DATA28 DATA27 DATA26 DATA25 DATA24 transistor pt36c gp714 diode GP113 transistor pt42c diode gp116 GP114 GP021 PT36c gp627 GP111

    pt45

    Abstract: No abstract text available
    Text: LatticeSC Family Data Sheet DS1004 Version 01.2, June 2006 LatticeSC Family Data Sheet Introduction June 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 110mW VCC12. LFSC25 900-Ball pt45

    PT35c transistor

    Abstract: pt35c transistor pt36c me 4946 PBGA PR25D transistor on 4409 307-45 4946 ah lm 458 ic
    Text: Data Addendum March 2002 ORCA OR3LxxxB Series Field-Programmable Gate Arrays Introduction This data addendum refers to the information found in the ORCA® Series 3C and 3T Field-Programmable Gate Arrays Data Sheet. • ■ Features ■ ■ ■ ■ ■ ■


    Original     		PDF 16-bit OR3L165B OR3L225B OR3L165B7PS208I-DB OR3L165B7PS240I-DB OR3L165B7BA352I-DB OR3L165B7BC432I-DB OR3L165B7BM680I-DB OR3L225B7BC432I-DB OR3L225B7BM680I-DB PT35c transistor pt35c transistor pt36c me 4946 PBGA PR25D transistor on 4409 307-45 4946 ah lm 458 ic

    transistor pt36c

    Abstract: datasheet transistor pt36C PT35c transistor pt36c microprocessor block diagram of plc pt35c transistor pt42c PT42C transistor BC 157 PLC Communication cables pin diagram
    Text: Data Sheet November, 2003 ORCA Series 4 FPGAs Introduction • Traditional I/O selections: — LVTTL 3.3V and LVCMOS (2.5 V and 1.8 V) I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability:


    Original     		PDF sink/12 transistor pt36c datasheet transistor pt36C PT35c transistor pt36c microprocessor block diagram of plc pt35c transistor pt42c PT42C transistor BC 157 PLC Communication cables pin diagram

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC/M Family Data Sheet DS1004 Version 02.1, June 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os • 700MHz global clock; 1GHz edge clocks


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC Family Data Sheet DS1004 Version 01.4b, February 2007 LatticeSC Family Data Sheet Introduction November 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW SC115

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC/M Family Data Sheet DS1004 Version 01.6, August 2007 LatticeSC/M Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW

    AL437

    Abstract: L97c L235C L103T L41C L140C L94C l165c L239C L43C
    Text: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC November 2003 Preliminary Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two


    Original     		PDF 8b/10b OIF-SPI4-02 ORSPI4-1FE1036IES ORSPI4-F1156IES ORSPI4-2FE1036CES ORSPI4-1FE1036CES ORSPI4-2F1156CES ORSPI4-1F1156CES AL437 L97c L235C L103T L41C L140C L94C l165c L239C L43C

    PT43C

    Abstract: PR41C pin diagram of ic 7495 shift register CORE F5A Y 928 K00 064 PT42C 21-INPUT pr46c OR4E10 k72 u2
    Text: Preliminary Data Sheet August 2000 ORCA Series 4 Field-Programmable Gate Arrays Programmable Features • ■ High-performance platform design. — 0.13 µm seven-level metal technology. — Internal performance of >250 MHz four logic levels . — I/O performance of >416 MHz for all user I/Os.


    Original     		PDF DS00-221FPGA PT43C PR41C pin diagram of ic 7495 shift register CORE F5A Y 928 K00 064 PT42C 21-INPUT pr46c OR4E10 k72 u2

    L130C

    Abstract: L74c l31c l97c l65c A311TC l146c l48c L202C L235C
    Text: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC May 2009 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two


    Original     		PDF 8b/10b OIF-SPI4-02 1156-fpBGA 1036-ball 6A-07 1036fpSBGA 1036-ftSBGA) 06x-09 1036-pin 1036-pin L130C L74c l31c l97c l65c A311TC l146c l48c L202C L235C

    transistor pt36c

    Abstract: pt36c PT35c transistor INTEL Core i5 760 PB7D pt35c k72 w5 OR3L165B8BM680-DB PB27A AL962
    Text: Data Addendum March 2002 ORCA OR3LxxxB Series Field-Programmable Gate Arrays Introduction • ■ Features ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.25 µm 5-level metal technology. 2.5 V internal supply voltage and 3.3 V I/O supply


    Original     		PDF 16-bit OR3L165B7BC432I-DB OR3L165B7BM680I-DB OR3L225B7BC432I-DB1 OR3L225B7BM680I-DB1 DA99-011FPGA DA99-008FPGA DS99-087FPGA) transistor pt36c pt36c PT35c transistor INTEL Core i5 760 PB7D pt35c k72 w5 OR3L165B8BM680-DB PB27A AL962

    2-bit comparator

    Abstract: LFSC3GA15E-5F900I PR77A PR55D pr94a diode transistor pt36c pt36C PB110C pb127d PB138
    Text: LatticeSC/M Family Data Sheet DS1004 Version 01.8, November 2007 LatticeSC/M Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW 2-bit comparator LFSC3GA15E-5F900I PR77A PR55D pr94a diode transistor pt36c pt36C PB110C pb127d PB138

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC Family Data Sheet DS1004 Version 01.5, March 2007 LatticeSC Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW LFSC25 FF1020 LFSC80

    Untitled

    Abstract: No abstract text available
    Text:  MachXO2 Breakout Board Evaluation Kit User’s Guide January 2014 Revision: EB68_02.2  MachXO2 Breakout Board Evaluation Kit User’s Guide Introduction Thank you for choosing the Lattice Semiconductor MachXO2 Breakout Board Evaluation Kit! This user’s guide describes how to start using the MachXO2 Breakout Board, an easy-to-use platform for evaluating and designing with the MachXO2 ultra-low density FPGA. Along with the board and accessories, this kit


    Original     		PDF MachXO2-7000HE MachXO2-12R16, RC0603JR-070RL CRCW06031R00JNEAHP RC0603FR-07100RL RC0402FR-071KL FT2232HL 93LC56C-I/SN LCMXO2-7000HE-4TG144C

    PB68C

    Abstract: LFSCM3GA40EP1
    Text: LatticeSC Family Data Sheet DS1004 Version 01.4a, January 2007 LatticeSC Family Data Sheet Introduction November 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW LVPECL33 SC115 PB68C LFSCM3GA40EP1

    Untitled

    Abstract: No abstract text available
    Text: Data Sheet January 3, 2002 ORCA Series 4 FPGAs Introduction • Traditional I/O selections: — LVTTL and LVCMOS 3.3 V, 2.5 V, and 1.8 V I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability:


    Original     		PDF sink/12 DS01-174NCIP DS01-024NCIP)

    transistor pt36c

    Abstract: stm cl-30 datasheet transistor pt36C transistor pt42c pt36c PT42C pt8a ap13.6 diode PT35c transistor PR25D
    Text: Data Sheet March, 2003 ORCA Series 4 FPGAs Introduction • Traditional I/O selections: — LVTTL 3.3V and LVCMOS (2.5 V and 1.8 V) I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability:


    Original     		PDF sink/12 OR4E06-1BM680I transistor pt36c stm cl-30 datasheet transistor pt36C transistor pt42c pt36c PT42C pt8a ap13.6 diode PT35c transistor PR25D

    L47C

    Abstract: L146C L135 l54c L62C L97C verilog code of prbs pattern generator L71C L235C L43C
    Text: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC February 2005 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two


    Original     		PDF 8b/10b OIF-SPI4-02 ORSPI4-2FE1036I ORSPI4-1FE1036I ORSPI4-2F1156I ORSPI4-1F1156I L47C L146C L135 l54c L62C L97C verilog code of prbs pattern generator L71C L235C L43C

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC Family Data Sheet DS1004 Version 01.3, August 2006 LatticeSC Family Data Sheet Introduction August 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 110mW

    transistor pt36c

    Abstract: PT18C datasheet transistor pt36C transistor pt42c pt36c pt35c transistor pt31C pt31c PL34C PT36c transistor
    Text: Preliminary Data Sheet December 2000 ORCA Series 4 Field-Programmable Gate Arrays Programmable Features • ■ High-performance platform design. — 0.13 µm seven-level metal technology. — Internal performance of >250 MHz four logic levels . — I/O performance of >416 MHz for all user I/Os.


    Original     		PDF DS01-024NCIP DS00-221FPGA) transistor pt36c PT18C datasheet transistor pt36C transistor pt42c pt36c pt35c transistor pt31C pt31c PL34C PT36c transistor

    pb127d

    Abstract: No abstract text available
    Text: LatticeSC/M Family Data Sheet DS1004 Version 02.2, December 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os • 700MHz global clock; 1GHz edge clocks


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW pb127d

    pt36c equivalent

    Abstract: PT21C CORE F5A k72 u2 128x8 rom
    Text: Data Sheet April, 2002 ORCA Series 4 FPGAs Introduction • Traditional I/O selections: — LVTTL and LVCMOS 3.3 V, 2.5 V, and 1.8 V I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability:


    Original     		PDF OR4E062BM680-DB OR4E061BA352-DB OR4E061BM680-DB OR4E04 OR4E06 DS01-174NCIP DS01-024NCIP) pt36c equivalent PT21C CORE F5A k72 u2 128x8 rom

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC/M Family Data Sheet DS1004 Version 01.9, January 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW

    CORE F5A

    Abstract: No abstract text available
    Text: Preliminary Data Sheet August 2000 m i c r o e le c t r o n ic s group Lucent Technologies Bell Labs Innovations ORCA Series 4 Field-Programmable Gate Arrays Programmable Features • High-performance platform design. — 0.13 pm seven-level metal technology.


    OCR Scan     		PDF DS00-221FPGA CORE F5A