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    IDTCSPUA877A Price and Stock

    Integrated Device Technology Inc IDTCSPUA877ABVG

    CSPUA877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Quest Components IDTCSPUA877ABVG 100
    • 1 $4.95
    • 10 $2.475
    • 100 $2.145
    • 1000 $2.145
    • 10000 $2.145
    		Buy Now

    IDTCSPUA877A Datasheets (5)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    IDTCSPUA877A Integrated Device Technology 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER Original PDF
    IDTCSPUA877ABVG Integrated Device Technology 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER Original PDF
    IDTCSPUA877ABVG8 Integrated Device Technology Clock/Timing - Application Specific, Integrated Circuits (ICs), IC PLL CLK DVR SDRAM 52-CABGA Original PDF
    IDTCSPUA877ANLG Integrated Device Technology 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER Original PDF
    IDTCSPUA877ANLG8 Integrated Device Technology Clock/Timing - Application Specific, Integrated Circuits (ICs), IC PLL CLK DVR SDRAM 40-VFQFPN Original PDF

    IDTCSPUA877A Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    CSPUA877

    Abstract: 2506036017Y0 CSPUA877A CUA877 IDTCSPUA877A
    Text: IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER IDTCSPUA877A DESCRIPTION: FEATURES: The CSPUA877A is a PLL based clock driver that acts as a zero delay buffer


    Original     		PDF IDTCSPUA877A CSPUA877A CSPUA877 2506036017Y0 CUA877 IDTCSPUA877A

    ULP877

    Abstract: IDTCSPUA877A MO-205 SSTU32864 ICS97ULP877 ICS98ULPA877A ICSSSTUB32871A D0-D20
    Text: ICSSSTUB32871A Integrated Circuit Systems, Inc. 27-Bit Registered Buffer for DDR2 Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A • Optimized for DDR2 400/533/667 JEDEC 4 Rank


    Original     		PDF ICSSSTUB32871A 27-Bit ICS98ULPA877A, ICS97ULP877, IDTCSPUA877A SSTU32864 ULP877 ULPA877A, IDTCSPUA877A MO-205 SSTU32864 ICS97ULP877 ICS98ULPA877A ICSSSTUB32871A D0-D20

    Untitled

    Abstract: No abstract text available
    Text: IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER IDTCSPUA877A FEATURES: DESCRIPTION: • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR2 Double Data Rate


    Original     		PDF IDTCSPUA877A 125MHz 410MHz IDTCSPUA877A CSPUA877A

    VFQFPN 28

    Abstract: No abstract text available
    Text: IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER IDTCSPUA877A DESCRIPTION: FEATURES: The CSPUA877A is a PLL based clock driver that acts as a zero delay buffer


    Original     		PDF IDTCSPUA877A IDTCSPUA877A 125MHz 410MHz 52-Ball 40-pin CUA877 VFQFPN 28

    Untitled

    Abstract: No abstract text available
    Text: ICSSSTUB32872A Integrated Circuit Systems, Inc. Advance Information 28-Bit Registered Buffer for DDR2 Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A • Optimized for DDR2 400/533/667 JEDEC 4 Rank


    Original     		PDF ICSSSTUB32872A 28-Bit ICS98ULPA877A, ICS97ULP877, IDTCSPUA877A SSTU32864 IDTCSPUA877A"

    CSPUA

    Abstract: 2506036017Y0 CSPUA877 CSPUA877A CUA877 IDTCSPUA877A
    Text: IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER IDTCSPUA877A DESCRIPTION: FEATURES: The CSPUA877A is a PLL based clock driver that acts as a zero delay buffer


    Original     		PDF IDTCSPUA877A CSPUA877A CSPUA 2506036017Y0 CSPUA877 CUA877 IDTCSPUA877A

    ICS97ULP877

    Abstract: ICS98ULPA877A ICSSSTUB32872A IDTCSPUA877A MO-205 SSTU32864
    Text: ICSSSTUB32872A Integrated Circuit Systems, Inc. Advance Information 28-Bit Registered Buffer for DDR2 Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A • Optimized for DDR2 400/533/667 JEDEC 4 Rank


    Original     		PDF ICSSSTUB32872A 28-Bit ICS98ULPA877A, ICS97ULP877, IDTCSPUA877A SSTU32864 IDTCSPUA877A" ICS97ULP877 ICS98ULPA877A ICSSSTUB32872A IDTCSPUA877A MO-205 SSTU32864

    Untitled

    Abstract: No abstract text available
    Text: IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER IDTCSPUA877A FEATURES: DESCRIPTION: • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR2 Double Data Rate


    Original     		PDF IDTCSPUA877A 125MHz 410MHz 52-Ball 40-pin IDTCSPUA877A CSPUA877A

    Untitled

    Abstract: No abstract text available
    Text: IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER IDTCSPUA877A FEATURES: DESCRIPTION: • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR2 Double Data Rate


    Original     		PDF IDTCSPUA877A 125MHz 410MHz 52-Ball 40-pin CSPUA877A

    Untitled

    Abstract: No abstract text available
    Text: ICSSSTUB32871A Integrated Circuit Systems, Inc. 27-Bit Registered Buffer for DDR2 Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A • Optimized for DDR2 400/533/667 JEDEC 4 Rank


    Original     		PDF ICSSSTUB32871A 27-Bit ICS98ULPA877A, ICS97ULP877, IDTCSPUA877A SSTU32864 ULP877 ULPA877A,

    J2 Q24A B

    Abstract: ICS98ULPA877A ICSSSTUAF32868A IDTCSPUA877A Q17A-Q20A
    Text: DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description ICSSSTUAF32868A QERR pin active low . The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity


    Original     		PDF 28-BIT ICSSSTUAF32868A before284 199707558G J2 Q24A B ICS98ULPA877A ICSSSTUAF32868A IDTCSPUA877A Q17A-Q20A

    THL W8

    Abstract: ICS98ULPA877A ICSSSTUAF32869A IDTCSPUA877A Q11A SSTU32864
    Text: DATASHEET ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description The ICSSSTUAF32869A includes a parity checking function. The ICSSSTUAF32869A accepts a parity bit from the memory controller at its input pin PARIN one or two cycles after the corresponding data input, compares it with


    Original     		PDF ICSSSTUAF32869A 14-BIT ICSSSTUAF32869A 199707558G THL W8 ICS98ULPA877A IDTCSPUA877A Q11A SSTU32864

    7103

    Abstract: ICS98ULPA877A IDT74SSTUBH32865A IDTCSPUA877A Q19A
    Text: DATASHEET IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 Description The IDT74SSTUBH32865A includes a parity checking function. The IDT74SSTUBH32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and


    Original     		PDF IDT74SSTUBH32865A 28-BIT IDT74SSTUBH32865A CLK284 199707558G 7103 ICS98ULPA877A IDTCSPUA877A Q19A

    ICS98ULPA877A

    Abstract: IDT74SSTUBF32868A IDTCSPUA877A Q22B
    Text: DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description occurred on the open-drain QERR pin active low . The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity,


    Original     		PDF 28-BIT cyc284 199707558G ICS98ULPA877A IDT74SSTUBF32868A IDTCSPUA877A Q22B

    Untitled

    Abstract: No abstract text available
    Text: DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description CONFIDENTIAL ICSSSTUAF32866B design of the ICSSSTUAF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is


    Original     		PDF 25-BIT ICSSSTUAF32866B 14-bit ICSSSTUAF32866B 199707558G

    THL W8

    Abstract: No abstract text available
    Text: DATASHEET 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description IDT74SSTUBF32869A The IDT74SSTUBF32869A includes a parity checking function. The IDT74SSTUBF32869A accepts a parity bit from the memory controller at its input pin PARIN one or two cycles after the corresponding data input, compares it


    Original     		PDF 14-BIT IDT74SSTUBF32869A IDT74SSTUBF32869A SSTU32864 199707558G THL W8

    schematic diagram atx Power supply 500w

    Abstract: pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS
    Text: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 Digital Signal Processors, iCoupler , iMEMS® and iSensor . . . . . 805, 2707, 2768-2769 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-568 RF Connectors . . . . . . . . . . . . . . . . . . . . . . Pages 454-455


    Original     		PDF P462-ND P463-ND LNG295LFCP2U LNG395MFTP5U US2011) schematic diagram atx Power supply 500w pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS

    ICS98ULPA877A

    Abstract: ICSSSTUAF32866B IDTCSPUA877A
    Text: DATASHEET ICSSSTUAF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the ICSSSTUAF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is


    Original     		PDF ICSSSTUAF32866B 25-BIT ICSSSTUAF32866B 14-bit 199707558G ICS98ULPA877A IDTCSPUA877A

    INSSTE32882

    Abstract: maxim dallas 2501 P16CV SY100EL16 SN65MLVD201 SN65EPT22 INCU877 INCUA877 ttl crystal oscillator using 7404 P16CV857B
    Text: Clocks and Timing Guide www.ti.com/clocks 2Q 2009 2 Clocks and Timing Guide ➔ Clocks and Timing Selection Tree Clocks by Function Clock Distribution Non- PLL Fanout Buffers PLL Buffers RF Synthesizers Clock Generation General Purpose Generator/Synthesizer


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: DATASHEET IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Description The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and


    Original     		PDF IDT74SSTUBF32865A 28-BIT IDT74SSTUBF32865A 199707558G

    IDTCSPUA877A

    Abstract: ICS98ULPA877A IDT74SSTUBF32868A
    Text: DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description occurred on the open-drain QERR pin active low . The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity,


    Original     		PDF 28-BIT cyc284 199707558G IDTCSPUA877A ICS98ULPA877A IDT74SSTUBF32868A

    ICS98ULPA877A

    Abstract: ICSSSTUAF32868A IDTCSPUA877A
    Text: DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description ICSSSTUAF32868A QERR pin active low . The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity


    Original     		PDF 28-BIT ICSSSTUAF32868A before284 199707558G ICS98ULPA877A ICSSSTUAF32868A IDTCSPUA877A

    Untitled

    Abstract: No abstract text available
    Text: DATASHEET IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the IDT74SSTUBF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is


    Original     		PDF IDT74SSTUBF32866B 25-BIT IDT74SSTUBF32866B 14-bit 199707558G

    INSSTE32882

    Abstract: maxim dallas 2501 insstua32866 INSSTU32864 INSSTU32866 ttl crystal oscillator using CIRCUIT DIAGRAM INCUA877 ps 2501 dallas GSM home automation block diagram INCU877
    Text: Clocks and Timing Guide www.ti.com/clocks 2Q 2009 2 Clocks and Timing Guide ➔ Clocks and Timing Selection Tree Clocks by Function Clock Distribution Non- PLL Fanout Buffers PLL Buffers RF Synthesizers Clock Generation General Purpose Generator/Synthesizer


    Original     		PDF