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    74F11 Search Results

    74F11 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SN74F11NSR Texas Instruments Triple 3-input positive-AND gates 14-SO 0 to 70 Visit Texas Instruments Buy
    SN74F112NE4 Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset 16-PDIP 0 to 70 Visit Texas Instruments Buy
    SN74F112N Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset 16-PDIP 0 to 70 Visit Texas Instruments Buy
    SN74F11D Texas Instruments Triple 3-input positive-AND gates 14-SOIC 0 to 70 Visit Texas Instruments Buy
    SN74F112NSR Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset 16-SO 0 to 70 Visit Texas Instruments Buy
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    74F11 Price and Stock

    Texas Instruments SN74F11DR

    IC GATE AND 3CH 3-INP 14SOIC
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    DigiKey SN74F11DR Cut Tape 2,490 1
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    SN74F11DR Digi-Reel 2,490 1
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    Mouser Electronics SN74F11DR 2,178
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    Chip1Stop SN74F11DR Cut Tape 2,425
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    Texas Instruments SN74F11N

    IC GATE AND 3CH 3-INP 14DIP
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    DigiKey SN74F11N Tube 2,120 1
    • 1 $0.62
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    Mouser Electronics SN74F11N 926
    • 1 $0.62
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    Newark SN74F11N Bulk 1
    • 1 $0.994
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    • 100 $0.833
    • 1000 $0.751
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    Texas Instruments SN74F11NSR

    IC GATE AND 3CH 3-INP 14SO
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    DigiKey SN74F11NSR Digi-Reel 2,000 1
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    SN74F11NSR Cut Tape 2,000 1
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    SN74F11NSR Reel 2,000 2,000
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    Mouser Electronics SN74F11NSR 1,983
    • 1 $0.6
    • 10 $0.38
    • 100 $0.309
    • 1000 $0.283
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    Texas Instruments SN74F112NSR

    IC FF JK TYPE DUAL 1BIT 16SO
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    DigiKey SN74F112NSR Digi-Reel 2,000 1
    • 1 $0.76
    • 10 $0.54
    • 100 $0.4251
    • 1000 $0.36497
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    SN74F112NSR Cut Tape 2,000 1
    • 1 $0.76
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    • 100 $0.4251
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    SN74F112NSR Reel 2,000 2,000
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    Mouser Electronics SN74F112NSR 1,967
    • 1 $0.76
    • 10 $0.486
    • 100 $0.397
    • 1000 $0.365
    • 10000 $0.306
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    Texas Instruments SN74F11D

    IC GATE AND 3CH 3-INP 14SOIC
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74F11D Tube 1,050 1
    • 1 $1.14
    • 10 $0.821
    • 100 $0.6555
    • 1000 $0.56871
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    NexGen Digital SN74F11D 275
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    Component Electronics, Inc SN74F11D 153
    • 1 $1.54
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    • 100 $1.15
    • 1000 $1
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    Find more 74F11 price and stock on Findchips.com

    74F11 Datasheets (97)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74F11 Fairchild Semiconductor Triple 3-Input AND Gate Original PDF
    74F11 Fairchild Semiconductor Triple 3-Input AND Gate Original PDF
    74F11 National Semiconductor Triple 3-Input AND Gate Original PDF
    74F11 Philips Semiconductors Triple 3-Input AND Gate Original PDF
    74F11 Philips Semiconductors Triple 3-input AND gate Original PDF
    74F112 Fairchild Semiconductor Dual JK Negative Edge-Triggered Flip-Flop Original PDF
    74F112 Fairchild Semiconductor Dual JK Negative Edge-Triggered Flip-Flop Original PDF
    74F112 Philips Semiconductors Dual J-K negative edge-triggered flip-flop Original PDF
    74F112 Signetics Dual JK Negative Edge Triggered Flip-Flop Scan PDF
    74F112CW Fairchild Semiconductor Dual JK Negative Edge-Triggered Flip-Flop Original PDF
    74F112DC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74F112PC Fairchild Semiconductor Dual JK Negative Edge-Triggered Flip-Flop Original PDF
    74F112PC Fairchild Semiconductor Dual JK Negative Edge-Triggered Flip-Flop Original PDF
    74F112PC National Semiconductor Dual JK Negative Edge-Triggered Flip-Flop Original PDF
    74F112PC Fairchild Semiconductor Dual JK Negative Edge-Triggered Flip-Flop Scan PDF
    74F112PC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74F112PC_NL Fairchild Semiconductor Dual JK Negative Edge-Triggered Flip-Flop Original PDF
    74F112PCQR Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74F112PCX Fairchild Semiconductor Dual JK Negative Edge-Triggered Flip-Flop Original PDF
    74F112QC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF

    74F11 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: General Description This device contains three independent gates, each of which performs the logic AND function. Ordering Code: Commercial Military Package Number 74F11PC N14A 54F11DM Note 2 J14A te See Section 0 Package Description 14-Lead (0.300" Wide) Molded Dual-In-Line


    Original     		PDF 54F/74F11 54F/74F11 74F11PC 54F11DM 54F11FM 54F11LM 74F11SC 74F11SJ DS009459-3

    74F113

    Abstract: 74F113PC 74F113SC 74F113SJ M14A M14D MS-001 N14A
    Text: Revised July 1999 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as long as


    Original     		PDF 74F113 74F113 74F113SC 14-Lead 74F113PC 74F113SC 74F113SJ M14A M14D MS-001 N14A

    jk flip flop

    Abstract: 74F114 74F114PC 74F114SC C1995 F114 M14A N14A
    Text: 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The ’F114 contains two high-speed JK flip-flops with common Clock and Clear inputs Synchronous state changes are initiated by the falling edge of the clock Triggering occurs at a voltage level of the clock and is not directly related


    Original     		PDF 74F114 jk flip flop 74F114 74F114PC 74F114SC C1995 F114 M14A N14A

    Untitled

    Abstract: No abstract text available
    Text: 54F11,74F11 Triple 3-Input AND Gate Literature Number: SNOS150A General Description This device contains three independent gates, each of which performs the logic AND function. Ordering Code: Commercial Military Package Number 74F11PC N14A 54F11DM Note 2


    Original     		PDF 54F11 74F11 SNOS150A 54F/74F11 54F/74F11 74F11PC 54F11DM 54F11FM 54F11LM

    74F114

    Abstract: N74F114D N74F114N
    Text: Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop with common clock and reset DESCRIPTION 74F114 PIN CONFIGURATION The 74F114, Dual Negative edge-triggered JK-Type Flip-Flop with common clock and reset inputs, features individual J, K, Clock CP ,


    Original     		PDF 74F114 74F114, SF00110 100MHz 500ns SF00006 74F114 N74F114D N74F114N

    74F11

    Abstract: 54F11DM 54F11FM 54F11LM 74F11PC 74F11SC 74F11SJ J14A M14A N14A
    Text: 54F 74F11 Triple 3-Input AND Gate General Description This device contains three independent gates each of which performs the logic AND function Commercial Package Number Military 74F11PC Package Description N14A 14-Lead 0 300 Wide Molded Dual-In-Line J14A


    Original     		PDF 74F11 74F11PC 14-Lead 14-Lead 74F11SC 74F11SJ 54F11FM 74F11 54F11DM 54F11FM 54F11LM 74F11PC 74F11SC 74F11SJ J14A M14A N14A

    E 94733

    Abstract: E 94733 3 74F113 74F113PC 74F113SC 74F113SJ C1995 F113 M14A M14D
    Text: 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The ’F113 offers individual J K Set and Clock inputs When the clock goes HIGH the inputs are enabled and data may be entered The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flip-flop will


    Original     		PDF 74F113 74F113PC 74F113SC 14-Lead E 94733 E 94733 3 74F113 74F113PC 74F113SC 74F113SJ C1995 F113 M14A M14D

    Untitled

    Abstract: No abstract text available
    Text: Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flops without reset FEATURE 74F113 PIN CONFIGURATION • Industrial temperature range available –40°C to +85°C CP0 1 14 VCC K0 2 13 CP1 DESCRIPTION The 74F113, dual negative edge-triggered JK-type flip-flop, features


    Original     		PDF 74F113 74F113, 500ns SF00006

    SF00106

    Abstract: SF00103
    Text: Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop FEATURE 74F112 PIN CONFIGURATION • Industrial temperature range available –40°C to +85°C CP0 1 16 VCC DESCRIPTION K0 2 15 RD0 The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop,


    Original     		PDF 74F112 74F112, 500ns SF00006 SF00106 SF00103

    schmitt trigger non inverting

    Abstract: 74F864 3 bit magnitude comparator 74F154 74F579 74F5300 equivalent multiplexer 30 pin QUAD D FLIP-FLOP "FAST TTL" 74*545
    Text: Philips Semiconductors Section 2 FAST TTL Logic Devices FAST TTL Logic Series CONTENTS 74F00 74F02 74F04 74F06 74F06A 74F07 74F07A 74F08 74F10 74F11 74F14 74F20 74F27 74F30 74F32 74F37 74F38 74F51 74F64 74F74 74F85 74F86 74F109 74F112 74F113 74F125 74F126


    Original     		PDF 74F00 74F02 74F04 74F06 74F06A 74F07 74F07A 74F08 74F10 74F11 schmitt trigger non inverting 74F864 3 bit magnitude comparator 74F154 74F579 74F5300 equivalent multiplexer 30 pin QUAD D FLIP-FLOP "FAST TTL" 74*545

    Untitled

    Abstract: No abstract text available
    Text: ADVANCE INFORMATION SN 54F114, SN 74F114 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET. COM MON CLEAR, AND COMMON CLOCK D2932, MARCH 1987 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil


    OCR Scan     		PDF 54F114, 74F114 D2932, 74F114 300-mil

    Untitled

    Abstract: No abstract text available
    Text: S E M IC O N D U C T O R tm 74F113 Dual JK Negative Edge-Triggered Flip-Flop Asynchronous input: G en eral D escrip tio n The ’F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be


    OCR Scan     		PDF 74F113

    KL SN 102

    Abstract: 74F113 74F113PC 74F113SC 74F113SJ M14A M14D MS-001 N14A
    Text: Revised July 1999 E M IC D N D U C T D R T M 74F113 Dual JK Negative Edge-Triggered Flip-Flop transferred to the outputs on the falling edge of the clock pulse. General Description T he 74F113 offers individual J, K, Set and C lo ck inputs. W hen the clock goes H IGH the inputs are enabled and


    OCR Scan     		PDF 74F113 74F113 KL SN 102 74F113PC 74F113SC 74F113SJ M14A M14D MS-001 N14A

    Untitled

    Abstract: No abstract text available
    Text: @ M OTOROLA Advance Information M C 5 4 F 1 1 4 M C 7 4 F 1 1 4 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP WITH COMMON CLOCKS AND CLEARS DESCRIPTION— MC54F/74F114 co nta in s tw o high-speed JK flip flo p s w ith co m m o n clock and Clear inputs. S yn ch ro n o us state


    OCR Scan     		PDF MC54F/74F114 MC54F/74F114

    Untitled

    Abstract: No abstract text available
    Text: S E M IC O N D U C T O R tm 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description Asynchronous input: The ’F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be


    OCR Scan     		PDF 74F113 74F113PC 14-Lead

    Untitled

    Abstract: No abstract text available
    Text: rnm ps oem iconaucior*-digneucs r A d i rro a u cis rro a u c i specmcauon Dual J - K negative edge-triggered flip-flops without reset 74F113 FEATURE TYPE TYPICAL fm, TYPICAL SUPPLY CURRENT* TOTAL • Industrial temperature range available -40°C to +85°C)


    OCR Scan     		PDF 74F113 100MHz 74F113, 500ns

    Untitled

    Abstract: No abstract text available
    Text: E M IC O N D U C T O R T 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description A synchronous Inputs: The ’F114 contains tw o high-speed JK flip-flops with com ­ mon C lock and C lear inputs. Synchronous state changes are


    OCR Scan     		PDF 74F114

    74F112

    Abstract: No abstract text available
    Text: E M I R ¡ C O C H April 1988 I L D N D U C T O Revised July 1999 R TM 74F112 Dual JK Negative Edge-Triggered Flip-Flop General Description Simultaneous LOW signals on S q and C q force both Q and The 74F112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state


    OCR Scan     		PDF 74F112

    Untitled

    Abstract: No abstract text available
    Text: Revised Ju ly 1999 S E M IC O N D U C T O R TM 74F11 Triple 3-Input AND Gate General Description This device contains three independent gates, each of w hich perform s the logic AND function. Ordering Code: Order Number Package Number Package Description 74F11SC


    OCR Scan     		PDF 74F11 74F11SC 74F11SJ 74F11PC 14-Lead S-120,

    Untitled

    Abstract: No abstract text available
    Text: 114 54F/74F114 Connection Diagrams Dual JK Negative Edge-Triggered Flip-Flop With Common Clocks and Clears Ki [ 7 i7 ] v c c 5 ~ r ~ L L Kt CP Jt 1 3] CP ' >- O C D S d i 0 Qi Qi H ] K2 • ji [7 Description s d i The 'F114 contains two high-speed JK flip-flops with common Clock and


    OCR Scan     		PDF 54F/74F114 54F/74F

    Untitled

    Abstract: No abstract text available
    Text: 11 54F/74F11 Triple 3-Input AND Gate Connection Diagrams Pin Assignment for DIP and SOIC Pin Assignment for LCC and PCC Ordering Code: See Section 5 Input Loading/Fan-Out: See Section 3 for U.L. definitions 54F/74F U.L. HIGH/LOW Description Pin Names Inputs


    OCR Scan     		PDF 54F/74F11 54F/74F 54F/74F

    74F10

    Abstract: 74F11 n74f10 N74F10D N74F10N N74F11D N74F11N
    Text: Philips Semiconductors-SigneHcs Document No. 853-0329 ECN No. 97683 Date o f issue September 2 0 ,1 98 9 Status Product Specification FAST 74F10, 74F11 Gates 74F10 Triple 3-Input NAND Gate 74F11 Triple 3-Input AND Gate FAST Products TYPE TYPICAL PROPAGATION


    OCR Scan     		PDF 74F10, 74F11 74F10 14-Pin N74F10N, N74F11N n74f10 N74F10D N74F10N N74F11D

    Untitled

    Abstract: No abstract text available
    Text: 112 54F/74F112 Connection Diagrams Dual J K Negative Edge-Triggered Flip-Flop CP- [7 Description The 'F112 contains two independent, high-speed J K flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock


    OCR Scan     		PDF 54F/74F112 54F/74F

    74F112

    Abstract: 74F112PC 74F112SC 74F112SJ M16A M16D MS-001 N16E h0023
    Text: Revised July 1999 E M IC D N D U C T D R T M 74F112 Dual JK Negative Edge-Triggered Flip-Flop General Description S im ultaneous LOW signals on S q and C q force both Q and T he 74F112 contains tw o independent, high-speed JK flip­ flops w ith D irect Set and C lear inputs. Synchronous state


    OCR Scan     		PDF 74F112 74F112 74F112PC 74F112SC 74F112SJ M16A M16D MS-001 N16E h0023