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    74F10 Search Results

    74F10 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SN74F1016DW Texas Instruments 16-Bit Schottky Barrier Diode R-C Bus-Termination Array 20-SOIC 0 to 70 Visit Texas Instruments Buy
    SN74F1056DR Texas Instruments 8-bit Schottky Barrier Diode Bus-Termination Array 16-SOIC 0 to 70 Visit Texas Instruments
    SN74F109N Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70 Visit Texas Instruments Buy
    SN74F10DR Texas Instruments Triple 3-input positive-NAND gates 14-SOIC 0 to 70 Visit Texas Instruments Buy
    SN74F109DR Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70 Visit Texas Instruments Buy
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    74F10 Price and Stock

    Texas Instruments SN74F10DR

    IC GATE NAND 3CH 3-INP 14SOIC
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    DigiKey SN74F10DR Cut Tape 2,496 1
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    SN74F10DR Digi-Reel 2,496 1
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    Mouser Electronics SN74F10DR 2,900
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    Rochester Electronics SN74F10DR 5,000 1
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    Texas Instruments SN74F10NSR

    IC GATE NAND 3CH 3-INP 14SO
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    DigiKey SN74F10NSR Cut Tape 1,870 1
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    SN74F10NSR Digi-Reel 1,870 1
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    Mouser Electronics SN74F10NSR 1,913
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    Texas Instruments SN74F10N

    IC GATE NAND 3CH 3-INP 14DIP
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    DigiKey SN74F10N Tube 1,195 1
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    Mouser Electronics SN74F10N 1,195
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    ComSIT Distribution SN74F10N 3,939
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    Component Electronics, Inc SN74F10N 1,372
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    Central Technologies CTCDRH74F-102M

    1000UH SMD SHIELDED PR INDUCTOR
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    DigiKey CTCDRH74F-102M Reel 1,010 1
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    Texas Instruments SN74F109D

    IC FF JK TYPE DUAL 1BIT 16SOIC
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    DigiKey SN74F109D Tube 629 1
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    Find more 74F10 price and stock on Findchips.com

    74F10 Datasheets (99)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74F10 Fairchild Semiconductor Triple 3-Input NAND Gate Original PDF
    74F10 Fairchild Semiconductor Triple 3-Input NAND Gate Original PDF
    74F10 National Semiconductor Triple 3-Input NAND Gate Original PDF
    74F10 National Semiconductor Triple 3-Input NAND Gate Original PDF
    74F10 Philips Semiconductors Triple 3-input NAND gate Original PDF
    74F104AI Bourns Fixed Inductors, Inductors, Coils, Chokes, CHOKE RF VARNISHED 100UH 10% Original PDF
    74F104AI-RC Bourns Axial Varnished Choke Original PDF
    74F1056 Fairchild Semiconductor 8-Bit Schottky Barrier Diode Array Original PDF
    74F1056 National Semiconductor 8-Bit Schottky Barrier Diode Array Original PDF
    74F1056SC Fairchild Semiconductor 8-Bit Schottky Barrier Diode Array Original PDF
    74F1056SCX Fairchild Semiconductor 8-Bit Schottky Barrier Diode Array Original PDF
    74F105AP Bourns Fixed Inductors, Inductors, Coils, Chokes, CHOKE RF VARNISHED 10UH 10% Original PDF
    74F105AP J.W. Miller Magnetics Inductor: RF: 10u: 10%: 7.96M: 50: Phenolic: 250m: Axial Original PDF
    74F105AP-RC Bourns Axial Varnished Choke Original PDF
    74F106AP Bourns Fixed Inductors, Inductors, Coils, Chokes, CHOKE RF VARNISHED 1UH 20% Original PDF
    74F106AP J.W. Miller Magnetics Inductor: RF: 1u: 20%: 7.96M: 45: Phenolic: 1000m: Axial Original PDF
    74F106AP-RC Bourns Axial Varnished Choke Original PDF
    74F1071 Fairchild Semiconductor 18-Bit Undershoot-Overshoot Clamp and ESD Protection Device Original PDF
    74F1071 Fairchild Semiconductor 18-Bit Undershoot-Overshoot Clamp and ESD Protection Device Original PDF
    74F1071 National Semiconductor 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device Original PDF

    74F10 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    motorola F74

    Abstract: 74F109
    Text: The MC54/74F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop refer to F74 data sheet by connecting the J and K inputs together.


    Original     		PDF MC54/74F109 motorola F74 74F109

    74F109

    Abstract: 9471 54F109DM 54F109FM 54F109LM 74F109PC 74F109SC 74F109SJ F109 J16A
    Text: 54F 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’F109 consists of two high-speed completely independent transition clocked JK flip-flops The clocking operation is independent of rise and fall times of the clock waveform The JK design allows operation as a D flip-flop refer to ’F74


    Original     		PDF 74F109 74F109PC 16-Lead 20-3A 74F109 9471 54F109DM 54F109FM 54F109LM 74F109PC 74F109SC 74F109SJ F109 J16A

    jedec MO-150

    Abstract: IEC-801-2 IEC801-2 jedec ms-013 74F1071SC IEC-801-2 ESD 74F1071 74F1071MSA 74F1071MSAX 74F1071MTC
    Text: Revised March 2005 74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device General Description Features The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to


    Original     		PDF 74F1071 18-Bit 74F1071 20-pin jedec MO-150 IEC-801-2 IEC801-2 jedec ms-013 74F1071SC IEC-801-2 ESD 74F1071MSA 74F1071MSAX 74F1071MTC

    74F109

    Abstract: 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E
    Text: Revised November 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.


    Original     		PDF 74F109 74F109SC 16-Lead MS-012, 74F109 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E

    150pf 6kv

    Abstract: 74F1071MTC 74F1071SC MO-150 MS-013 MSA20 MTC20 74F1071 74F1071MSA
    Text: 74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device Features General Description • 18-bit array structure in 20-pin package The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress


    Original     		PDF 74F1071 18-Bit 20-pin 74F1071 20-Lead 150pf 6kv 74F1071MTC 74F1071SC MO-150 MS-013 MSA20 MTC20 74F1071MSA

    74F1056

    Abstract: 74F1056SC C1995 M16A b50 diode
    Text: 74F1056 8-Bit Schottky Barrier Diode Array General Description Features The ’F1056 is an 8-bit Schottky barrier diode array designed to be employed as termination on the inputs to memory bus lines or CLOCK lines This device is designed to suppress negative transients caused by line reflections switching


    Original     		PDF 74F1056 F1056 74F1056SC 16-Lead 74F1056 74F1056SC C1995 M16A b50 diode

    74F109

    Abstract: F109 74F109PC 74F109SC 74F109SJ M16A M16D MS-001 N16E 74f109 fairchild
    Text: Revised September 2000 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.


    Original     		PDF 74F109 74F109SC 16-Lead MS-012, 74F109 F109 74F109PC 74F109SC 74F109SJ M16A M16D MS-001 N16E 74f109 fairchild

    schmitt trigger non inverting

    Abstract: 74F864 3 bit magnitude comparator 74F154 74F579 74F5300 equivalent multiplexer 30 pin QUAD D FLIP-FLOP "FAST TTL" 74*545
    Text: Philips Semiconductors Section 2 FAST TTL Logic Devices FAST TTL Logic Series CONTENTS 74F00 74F02 74F04 74F06 74F06A 74F07 74F07A 74F08 74F10 74F11 74F14 74F20 74F27 74F30 74F32 74F37 74F38 74F51 74F64 74F74 74F85 74F86 74F109 74F112 74F113 74F125 74F126


    Original     		PDF 74F00 74F02 74F04 74F06 74F06A 74F07 74F07A 74F08 74F10 74F11 schmitt trigger non inverting 74F864 3 bit magnitude comparator 74F154 74F579 74F5300 equivalent multiplexer 30 pin QUAD D FLIP-FLOP "FAST TTL" 74*545

    IEC-801-2 ESD

    Abstract: 74F1071 74F1071MSA 74F1071MTC 74F1071SC MSA20 MTC20
    Text: 74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device General Description The ’F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge ESD . The inputs of the device aggressively


    Original     		PDF 74F1071 18-Bit F1071 20-pin 74omer IEC-801-2 ESD 74F1071 74F1071MSA 74F1071MTC 74F1071SC MSA20 MTC20

    751A-02

    Abstract: 74F10 74f10 motorola
    Text: MC54/74F10 TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE FAST SCHOTTKY TTL VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 7 14 1 GND N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC54FXXJ MC74FXXN


    Original     		PDF MC54/74F10 51A-02 MC54FXXJ MC74FXXN MC74FXXD 54/74F 751A-02 74F10 74f10 motorola

    dual d flip-flop

    Abstract: t flipflop 74F109
    Text: MOTOROLA DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC54/74F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking_operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D


    OCR Scan     		PDF MC54/74F109 dual d flip-flop t flipflop 74F109

    74f740

    Abstract: 74F5074D
    Text: Philip* Semlconductora-Signetic* FAST Producto Product »pacification Synchronizing dual J - K positive edge-triggered flip-flop with metastable immune characteristics FEATURE • Pinout compatible with 74F109 • Metastable immune characteristics • Output skew guaranteed less than 1.5ns


    OCR Scan     		PDF 74F50109 74F109 74F5074 74F50728 See74F50729 150MHz 500ns 74f740 74F5074D

    Untitled

    Abstract: No abstract text available
    Text: EM IC O N D U C T O R T 74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device Fast bipolar voltage clam ping action General Description Dual ce nte r pin grounds fo r min inductance The ’F1071 is an 18-bit undershoot/overshoot clam p which


    OCR Scan     		PDF 74F1071 18-Bit F1071 arra888-522-5372

    a215c

    Abstract: 74F109 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E
    Text: A p riM 9 8 8 Revised January 1999 74F109^ Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to Cp sets Q to LOW level T he F 1 09 consists of tw o high-speed, com pletely indepen­ dent transition clocked JK flip-flops. The clocking operation


    OCR Scan     		PDF 74F109^ a215c 74F109 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E

    Untitled

    Abstract: No abstract text available
    Text: 10 54F/74F10 Triple 3-Input NAND Gate Connection Diagrams NC NC 0 B 0 ÎÎ 0 Ordering Code: See S ection 5 Pin Assignment for LCC and PCC Pin Assignment for DIP and SOIC Input Loading/Fan-Out: See S ection 3 fo r U.L. d e fin itio n s 54F/74F U.L. Description


    OCR Scan     		PDF 54F/74F10 54F/74F 54F/74F

    74F109

    Abstract: No abstract text available
    Text: *p n l1 9 , æ Revised January 1999 SEMICONDUCTOR TM 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to C q sets Q to LOW level The F109 consists of tw o high-speed, com pletely indepen­ den t transition clocked JK flip-flops. The clocking operation


    OCR Scan     		PDF 74F109 74F109SC 74F109SJ 74F109PC

    74F10

    Abstract: 74F11 n74f10 N74F10D N74F10N N74F11D N74F11N
    Text: Philips Semiconductors-SigneHcs Document No. 853-0329 ECN No. 97683 Date o f issue September 2 0 ,1 98 9 Status Product Specification FAST 74F10, 74F11 Gates 74F10 Triple 3-Input NAND Gate 74F11 Triple 3-Input AND Gate FAST Products TYPE TYPICAL PROPAGATION


    OCR Scan     		PDF 74F10, 74F11 74F10 14-Pin N74F10N, N74F11N n74f10 N74F10D N74F10N N74F11D

    74F109

    Abstract: No abstract text available
    Text: Product specification Philips Semiconductors-Signetics FAST Products Positive J -K positive edge-triggered flip-flops FEATURE TYPE • Industrial temperature range available -40°C to +85°C 74F109 DESCRIPTION The 74F109 is a dual positive edgetriggered JK-type flip-flop featuring in­


    OCR Scan     		PDF 74F109 74F109 40-pin VSO-40) 1CC0-13â 56-pin VSO-56) B/B44 44-pin

    8 pin dip j k flipflop ic

    Abstract: 74f728 Toggle flip flop IC 74F729 74F109A kO314 74F109 N74F109AD N74F109AN internal diagram of jk flipflop
    Text: FAST 74F109A FLIP-FLOP Synchronizing Dual J-K Positive Edge-Triggered Flip-Flops Preliminary Specification FEATURES • Metastable Immune Characteris­ tics • Same pinout and function as 74F109 • See 74F74A for Synchronizing Dual D-Type Flip-Flop • See 74F728 for Synchronizing


    OCR Scan     		PDF 74F109A 74F109 74F74A 74F728 74F729 74F109A 500ns 8 pin dip j k flipflop ic Toggle flip flop IC kO314 74F109 N74F109AD N74F109AN internal diagram of jk flipflop

    Untitled

    Abstract: No abstract text available
    Text: o o> National Semiconductor 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: LOW input to S d sets Q to HIGH level LOW input to C q sets Q to LOW level Clear and Set are independent of clock _ Simultaneous LOW on C q and S q makes both Q and Q


    OCR Scan     		PDF 54F/74F109

    74F1050

    Abstract: 9.D8
    Text: ADVANCE INFORMATION Semiconductor 1050 ß National 74F1050 12-Bit Schottky Barrier Diode Array General Description Features The ’F1050 is a 12-bit Schottky barrier diode array designed to be employed as termination on the inputs to memory bus lines or CLOCK lines. This device is designed to suppress


    OCR Scan     		PDF 74F1050 12-Bit F1050 74F1050SC 16-Lead D04D5- 9.D8

    74F10

    Abstract: No abstract text available
    Text: Signetics FAST 74F10, 74F11 Gates 74F10 Triple 3-Input NAND Gate 74F11 Triple 3-Input AND Gate FAST Products Product Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT T O T A L 74F10 3.5ns 3.3mA 74F11 4.2ns 5.3mA ORDERING INFORMATION COMMERCIAL RANGE


    OCR Scan     		PDF 74F10, 74F11 74F10 74F11 N74F10N, N74F11N N74F10D, N74F11D

    Untitled

    Abstract: No abstract text available
    Text: National Semiconductor 54F/74F10 Triple 3-Input NAND Gate Ordering Code: see section5 Connection Diagrams Logic Symbol Pin A ssignm ent fo r DIP, SOIC and Flatpak IE E E /IE C *0 - Pin A ssignm ent fo r LCC and PCC C, NC B, NC A, , W 14 2 E l E B m GD


    OCR Scan     		PDF 54F/74F10

    74F109

    Abstract: No abstract text available
    Text: Signetics 74F109 FLIP-FLOP Dual J-K Positive Edge-Triggered Flip-Flops FAST Products DESCRIPTION The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, Clock, Set and Reset inputs; also true and complementary outputs. Set S . and Reset (R ) are asynchronous


    OCR Scan     		PDF 74F109 74F109 500ns