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    TQ144 Price and Stock

    Lattice Semiconductor Corporation ICE40HX1K-TQ144

    IC FPGA 96 I/O 144TQFP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey ICE40HX1K-TQ144 Tray 2,458 1
    • 1 $8.4
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    Newark ICE40HX1K-TQ144 Bulk 134 1
    • 1 $8.74
    • 10 $8.16
    • 100 $7.5
    • 1000 $7.3
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    Win Source Electronics ICE40HX1K-TQ144 2,977
    • 1 -
    • 10 $11.1793
    • 100 $7.4529
    • 1000 $7.4529
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    Lattice Semiconductor Corporation ICE40HX4K-TQ144

    IC FPGA 107 I/O 144TQFP
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    DigiKey ICE40HX4K-TQ144 Tray 290 1
    • 1 $10.2
    • 10 $10.2
    • 100 $10.2
    • 1000 $8.1875
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    Newark ICE40HX4K-TQ144 Bulk 112 1
    • 1 $10.61
    • 10 $9.93
    • 100 $9.31
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    Win Source Electronics ICE40HX4K-TQ144 1,040
    • 1 -
    • 10 $11.1197
    • 100 $9.0348
    • 1000 $9.0348
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    AMD XCR3256XL-10TQ144I

    IC CPLD 256MC 9.1NS 144TQFP
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    DigiKey XCR3256XL-10TQ144I Tray 37 1
    • 1 $64.63
    • 10 $64.63
    • 100 $64.63
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    AMD XCV50-4TQ144C

    IC FPGA 98 I/O 144TQFP
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    DigiKey XCV50-4TQ144C Tray
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    Microchip Technology Inc M2GL005-TQ144

    IC FPGA 84 I/O 144TQFP
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    DigiKey M2GL005-TQ144 Tray
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    NAC M2GL005-TQ144 Tray 60
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    Find more TQ144 price and stock on Findchips.com

    TQ144 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    QF32

    Abstract: FG320 FF668 BF957 FF1513 CP132 PQ100 FF1148 TQ144 TQ176
    Text: TQFP VQFP TQ176 TQ160 TQ144 TQ100 22.0 x 22.0 mm 0.5 mm 26.0 x 26.0 mm (0.5 mm) 26.0 x 26.0 mm (0.5 mm) VQ64 12.0 x 12.0 mm (0.8 mm) 12.0 x 12.0 mm (0.5 mm) 9/18/07 16.0 x 16.0 mm (0.5 mm) VQ100 VQ44 MPM_1498_pmatrices_Q307_r1.qxd 22 16.0 x 16.0 mm (0.5 mm)


    Original     		PDF TQ176 TQ160 TQ144 TQ100 VQ100 HQ/PQ208 HQ304 HQ/PQ240 HQ/PQ160 PQ100 QF32 FG320 FF668 BF957 FF1513 CP132 PQ100 FF1148 TQ144 TQ176

    TQ144

    Abstract: HQFP HT100 HT176 PK009 TQ100 TQ176
    Text: R PK009 v1.0 June 1, 2000 TQFP (TQ100, TQ144, TQ176) Packages HQFP (Heat Sink) (HT100, HT144, HT176) Packages 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.


    Original     		PDF PK009 TQ100, TQ144, TQ176) HT100, HT144, HT176) TQ144 HQFP HT100 HT176 PK009 TQ100 TQ176

    TQ144

    Abstract: TQ176 TQ-144 HT176 TQ100 HT100 HT144 HT-100 package drawings
    Text: Package Drawings TQFP/HTQFP Packages - TQ100, TQ144, TQ176, HT100, HT144, HT176 10-28 November 13, 1997 Version 1.2


    Original     		PDF TQ100, TQ144, TQ176, HT100, HT144, HT176 TQ144 TQ176 TQ-144 HT176 TQ100 HT100 HT144 HT-100 package drawings

    TQG144

    Abstract: tq144 PK009
    Text: R TQFP TQ144/TQG144 Package PK009 (v1.2) June 18, 2004 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.


    Original     		PDF TQ144/TQG144) PK009 TQG144 tq144 PK009

    XC9572

    Abstract: XC9572-10PC44C xc9572-15PQ100 15PC44I xc9572 data sheet XC9572-7PC44C PC44 PC84 xc9572-10pq100c XC9572-15PC84C
    Text: XC9572 In-System Programmable CPLD R DS065 v4.2 April 15, 2005 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V in-system programmable


    Original     		PDF XC9572 DS065 36V18 XC9572-10PC44C xc9572-15PQ100 15PC44I xc9572 data sheet XC9572-7PC44C PC44 PC84 xc9572-10pq100c XC9572-15PC84C

    XCR3128XL-10VQ100I

    Abstract: XCR3128XL-10TQ144I XCR3128XL-7CS144I XCR3128XL XCR3128XL-10CS144I XCR3128XL-10VQ100C CS144 marking E13 diode L12M1 k3296
    Text: R XCR3128XL 128 Macrocell CPLD DS016 v2.1 August 21, 2003 14 Preliminary Product Specification Features Description • Low power 3.3V 128 macrocell CPLD • 6.0 ns pin-to-pin logic delays • System frequencies up to 175 MHz • 128 macrocells with 3,000 usable gates


    Original     		PDF XCR3128XL DS016 144-pin 144-ball 100-pin XCR3128XL-10VQ100I XCR3128XL-10TQ144I XCR3128XL-7CS144I XCR3128XL-10CS144I XCR3128XL-10VQ100C CS144 marking E13 diode L12M1 k3296

    XC3S700A

    Abstract: xc3s200aft256 XC3S400AFT256 XC3S50A L01P L02P FG320 UG331 L05P xc3s400a ftg256
    Text: Spartan-3A FPGA Family: Data Sheet R DS529 July 10, 2007 Product Specification Module 1: Introduction and Ordering Information - DS529-1 v1.4.1 July 10, 2007 • • • • • • • Introduction Features Architectural and Configuration Overview General I/O Capabilities


    Original     		PDF DS529 DS529-1 DS529-2 DS529-3 XC3S50A XC3S200A FT256 DS529-4 XC3S700A xc3s200aft256 XC3S400AFT256 L01P L02P FG320 UG331 L05P xc3s400a ftg256

    XC95144XL-10TQ144I

    Abstract: XC95144XL-10TQG100C XAPP114 XAPP427 XC9500XL XC95144 XC95144XL XC95144XL-5-CS144 XC95144XL-5TQ100 xc95144xl tq144
    Text: XC95144XL High Performance CPLD R DS056 v1.8 July 15, 2005 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell


    Original     		PDF XC95144XL DS056 XC9500XL CS144 220oC. XC95144XL-10TQ144I XC95144XL-10TQG100C XAPP114 XAPP427 XC95144 XC95144XL-5-CS144 XC95144XL-5TQ100 xc95144xl tq144

    Untitled

    Abstract: No abstract text available
    Text: iCE40 LP/HX Family Data Sheet DS1040 Version 02.9, April 2014 iCE40 LP/HX Family Data Sheet Introduction February 2014 Data Sheet DS1040 Features  Flexible Logic Architecture – Schmitt trigger inputs, to 200 mV typical hysteresis • Programmable pull-up mode


    Original     		PDF iCE40â DS1040 iCE40 DS1040 LP384

    transistor bl p89

    Abstract: bl p74 transistor J955 XC4000 XC4000A XC4000D XC4000E XC4000EX XC4000H p180 g8
    Text: book XC4000E and XC4000X Series Field Programmable Gate Arrays R January 29, 1999 Version 1.5 6* XC4000E and XC4000X Series Features Note: XC4000 Series devices described in this data sheet include the XC4000E family and XC4000X Series. XC4000X Series devices described in this data sheet


    Original     		PDF XC4000E XC4000X XC4000 XC4000EX XC4000XL transistor bl p89 bl p74 transistor J955 XC4000A XC4000D XC4000H p180 g8

    XAPP393

    Abstract: DS090 VQ100 XC2C128 XC2C256 XC2C32 XC2C384 XC2C64 interfacing 8051 XC9500 cpld pins table
    Text: R CoolRunner-II CPLD Family DS090 v1.7 October 2, 2003 Preliminary Product Specification Features • • • • Optimized for 1.8V systems - Industry’s fastest low power CPLD - Static Icc of less than 100 microamps at all times - Densities from 32 to 512 macrocells


    Original     		PDF DS090 IEEE1149 f/wp170 XAPP393 DS090 VQ100 XC2C128 XC2C256 XC2C32 XC2C384 XC2C64 interfacing 8051 XC9500 cpld pins table

    SPARTAN-3 XC3S400 PQ208

    Abstract: SPARTAN-3 XC3S400 pq208 architecture SPARTAN-3 XC3S400 tq144 SPARTAN-3 XC3S400 Spartan-3 FPGA Family XC3S4000-FG676 SPARTAN-3 XC3S400 pin SPARTAN-3 XC3S400 architecture XC3S4000FG676 XILINX SPARTAN VQG100
    Text: 06 Spartan-3 FPGA Family: Introduction and Ordering Information R DS099-1 v1.4 January 17, 2005 Preliminary Product Specification Introduction - The Spartan -3 family of Field-Programmable Gate Arrays is specifically designed to meet the needs of high volume,


    Original     		PDF DS099-1 XC3S50CP132, XC3S2000FG456, XC3S4000FG676 DS099-1, DS099-2, DS099-3, DS099-4, DS313, DS314-1, SPARTAN-3 XC3S400 PQ208 SPARTAN-3 XC3S400 pq208 architecture SPARTAN-3 XC3S400 tq144 SPARTAN-3 XC3S400 Spartan-3 FPGA Family XC3S4000-FG676 SPARTAN-3 XC3S400 pin SPARTAN-3 XC3S400 architecture XILINX SPARTAN VQG100

    xc2s300e pinouts

    Abstract: LP1-D12 L43P xc2s300e l36n xc2s50e L26N L28N XC2S200E L18P
    Text: Spartan-IIE 1.8V FPGA Family: Pinout Tables R DS077-4 v1.0 November 15, 2001 Preliminary Product Specification Pin Definitions Dedicated Pin Direction Description GCK0, GCK1, GCK2, GCK3 No Input Clock input pins that connect to Global Clock buffers. These pins


    Original     		PDF DS077-4 thT11 DS001-1, DS001-2, DS001-3, DS001-4, xc2s300e pinouts LP1-D12 L43P xc2s300e l36n xc2s50e L26N L28N XC2S200E L18P

    XC3S700AN FGG484

    Abstract: XC3S400AN-FGG400 XC3S700A FGG484 xc3s200an XC3S400AN FGG400 FGG676 SPARTAN 3an XC3S50A XC3S700AN-FG484 XC3S700AN
    Text: Spartan-3AN FPGA Family Data Sheet R DS557 June 2, 2008 Module 1: Introduction and Ordering Information - DS557-1 v3.1 June 2, 2008 • • • • • • • • Introduction Features Architectural Overview Configuration Overview In-system Flash Memory Overview


    Original     		PDF DS557 DS557-1 XC3S50AN. XC3S700AN FG484 XC3S1400AN FGG676 DS557-4 XC3S700AN FGG484 XC3S400AN-FGG400 XC3S700A FGG484 xc3s200an XC3S400AN FGG400 SPARTAN 3an XC3S50A XC3S700AN-FG484

    XC9572XL

    Abstract: PC44 VQ44 XC9500 XC9500XL XC95144XL XC95288XL XC9536XL XC95288XL pinout
    Text: k XC9500XL High-Performance CPLD Family Data Sheet R DS054 v2.5 May 22, 2009 Product Specification Features • • Optimized for high-performance 3.3V systems - 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz - Small footprint packages including VQFPs, TQFPs


    Original     		PDF XC9500XL DS054 XC9572XL PC44 VQ44 XC9500 XC95144XL XC95288XL XC9536XL XC95288XL pinout

    XC3S200A

    Abstract: xilinx XC3S200A tmds fpga xc3s1400a FG484 Spartan-3A FPGA 1400k FG320 SPARTAN-3A XC3S50A XC3S700A
    Text: SPARTAN-3 GENERATION FPGAs Xilinx Spartan -3A FPGA Platform The World’s Lowest-Cost I/O Optimized FPGAs The Programmable Logic Challenge of I/O Intensive Designs • Traditional FPGAs are proportionate between logic and I/O not being costeffective for I/O intensive designs


    Original     		PDF SpartanFG320 FG400 FG484 FG676 XC3S200A xilinx XC3S200A tmds fpga xc3s1400a FG484 Spartan-3A FPGA 1400k FG320 SPARTAN-3A XC3S50A XC3S700A

    XC95108

    Abstract: XC95108-10PQ160C xc95108-10pqg100i XC95108-20PQG160I TQG100 XC95108-15PC84C PGC84 XC95108-20PQ100I
    Text: – PRODUCT OBSOLETE / UNDER OBSOLESCENCE – XC95108 In-System Programmable CPLD R DS066 v5.0 May 17, 2013 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 108 macrocells with 2,400 usable gates


    Original     		PDF XC95108 DS066 36V18 PQ160 XCN11010 XC95108-10PQ160C xc95108-10pqg100i XC95108-20PQG160I TQG100 XC95108-15PC84C PGC84 XC95108-20PQ100I

    Untitled

    Abstract: No abstract text available
    Text: Revision 15 ProASIC3 Flash Family FPGAs with Optional Soft ARM Support Features and Benefits Advanced I/O High Capacity • 15 K to 1 M System Gates • Up to 144 Kbits of True Dual-Port SRAM • Up to 300 User I/Os Reprogrammable Flash Technology • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS


    Original     		PDF 130-nm, 64-Bit 128-Bit

    XC9536XL

    Abstract: XAPP114 XAPP427 XC9500XL XC9536 Pb-Free Marking Codes XC9536XL VQFP XC9536XL-10VQ64C VQG44 XC9536XL-10VQ44
    Text: XC9536XL High Performance CPLD R DS058 v1.7 July 15, 2005 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell


    Original     		PDF XC9536XL DS058 XC9500XL 220oC. XAPP114 XAPP427 XC9536 Pb-Free Marking Codes XC9536XL VQFP XC9536XL-10VQ64C VQG44 XC9536XL-10VQ44

    qfn 3x3 tray dimension

    Abstract: XCDAISY BFG95 XC5VLX330T-1FF1738I pcb footprint FS48, and FSG48 WS609 jedec so8 Wire bond gap XC3S400AN-4FG400I FFG676 XC4VLX25 cmos 668 fcbga
    Text: Device Package User Guide [Guide Subtitle] [optional] UG112 v3.5 November 6, 2009 [optional] R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		PDF UG112 UG072, UG075, XAPP427, qfn 3x3 tray dimension XCDAISY BFG95 XC5VLX330T-1FF1738I pcb footprint FS48, and FSG48 WS609 jedec so8 Wire bond gap XC3S400AN-4FG400I FFG676 XC4VLX25 cmos 668 fcbga

    CQ256

    Abstract: CQ208 4PMX 4pm smd
    Text: te /e • / Speed Grade JTAG I/O 3.3 Volt 5 Volt PCI 5.0 Volt Tolerant at 3.3V VQ100 Std, - 1 , - 2 , - 3 129 8,000 256 512 - — Yes Yes — — Yes PQ208 Std, - 1 , - 2 , - 3 129 8,000 256 512 — — Yes Yes — — Yes TQ144 Std, - 1 , - 2 , - 3 129 8,000


    OCR Scan     		PDF A54SX08 VQ100 PQ208 TQ144 TQ176 1P1280A RP14100A RT1020 RT1280A RT1425A CQ256 CQ208 4PMX 4pm smd

    I-CUBE

    Abstract: P005 p055 TRANSISTOR IDS200 p055 power transistor IQ32B IQ48 IQ64B IQ96 84l transistor
    Text: I-Cube IQ Family Data Sheet m F eatures D e s c r ip t io n • SRAM-based, in-system programmable The IQ family of SRAM-based bit-oriented switching devices is • Switch Matrix manufactured using 0.6|jm CMOS processes. These devices — Non-Blocking offer clock speeds of up to 150 MHz and pin-to-pin delay as low


    OCR Scan     		PDF IQ32B-TQ52 IQ64B IQ32B 144PQ 100TQ 144TQ I-CUBE P005 p055 TRANSISTOR IDS200 p055 power transistor IQ32B IQ48 IQ96 84l transistor

    Untitled

    Abstract: No abstract text available
    Text: flX IU N X Spartan and S p artan X l Families Field Programmable Gate Arrays September 28, 1998 Version 1.2 Preliminary Product Specification Introduction • System level features - Available in both 5.0 Volt and 3.3 Volt versions - On-chip SelectRAM memory


    OCR Scan     		PDF SpartaXCS20XL-4 PQ208C PQ208

    Untitled

    Abstract: No abstract text available
    Text: Spartan and SpartanXL Families Field Programmable Gate Arrays £ XILINX January 6 , 1999 Version 1.4 Prelim inary Product Specification Introduction • The S partan Series is the first high-volum e production FPGA solution to deliver all the key requirem ents for ASIC


    OCR Scan     		PDF 5M-1994 M0-151-BAL-2