GSR-V
Abstract: DIP20 M5913 M5913B1
Text: M5913 COMBINED SINGLE CHIP PCM CODEC AND FILTER SYNCHRONOUS CLOCKS ONLY AT&T D3/D4 AND CCITT COMPATIBLE TWO TIMING MODES: FIXED DATA RATE MODE 1.536MHz, 1.544MHz, 2.048MHz VARIABLE DATA MODE: 64KHz - 4.096MHz PIN SELECTABLE µ-LAW OR A-LAW OPERATION NO EXTERNAL COMPONENTS FOR SAMPLE-AND-HOLD AND AUTO ZERO FUNCTIONS
|
Original
|
PDF
|
M5913
536MHz,
544MHz,
048MHz
64KHz
096MHz
M5913
M5913-Digital
M5913B1
GSR-V
DIP20
M5913B1
|
LG 631 IC
Abstract: SDXC pin diagram of tle 7203 F804 F808 HSP50216 HSP50216KI tle 8209 e SD2C tle 8209
Text: HSP50216 TM Data Sheet tle P5 6 jec rnn ra abl ital n ver tho w rsi por n, ico cto Four-Channel Programmable Digital DownConverter The HSP50216 Quad Programmable Digital DownConverter QPDC) is designed for high dynamic range applications such as cellular basestations where multiple channel processing is
|
Original
|
PDF
|
HSP50216
HSP50216
16-bit
LG 631 IC
SDXC
pin diagram of tle 7203
F804
F808
HSP50216KI
tle 8209 e
SD2C
tle 8209
|
tilex
Abstract: i7-600 Mobile GFX 2BA
Text: Intel Core i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series Datasheet — Volume Two This is volume 2 of 2. Refer to Document Number 322812 for Volume 1 November 2010 Document Number: 322813-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
|
Original
|
PDF
|
i7-600,
i5-500,
i5-400
i3-300
410-41Fh
D884C70067DFC104BFDF8368D7254DBBh
D884C70
067DFC1
04BFDF8
368D725
tilex
i7-600 Mobile
GFX 2BA
|
hdlc
Abstract: ITB00728 ITL00726 ITP00727 ITP03527 smd marking code A06
Text: ICs for Communications ISDN D-Channel Exchange Controller IDEC PEB 2075 User´s Manual 05.92 PEB 2075 Revision History: Page 05.92 Subjects (changes since last revision) Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible
|
Original
|
PDF
|
P-DIP-28
P-LCC-44
hdlc
ITB00728
ITL00726
ITP00727
ITP03527
smd marking code A06
|
diagram receiver and transmitter for microcontroller
Abstract: hdlc PEB 2075-N ITB00728 EPIC-1
Text: ISDN D-Channel Exchange Controller IDEC PEB 2075 General Description With the IOM-2 interface, designers have more flexibility with respect to handling of D-channel information. Layer-1 transceivers are connected over the IOM-2 interface directly to either the PEB 2055 (EPIC-1) or the PEB 2054 (EPIC-S).
|
Original
|
PDF
|
2075-N
P-LCC-44-1
2075-P
P-DIP-28-1
ITB00728
diagram receiver and transmitter for microcontroller
hdlc
PEB 2075-N
ITB00728
EPIC-1
|
Untitled
Abstract: No abstract text available
Text: HSP50216 Data Sheet August 17, 2007 Four-Channel Programmable Digital Downconverter FN4557.6 Features • Up to 70MSPS Input The HSP50216 Quad Programmable Digital Downconverter QPDC is designed for high dynamic range applications such as cellular basestations where multiple channel
|
Original
|
PDF
|
HSP50216
FN4557
70MSPS
HSP50216
16-bit
|
2180f3
Abstract: 2180F TISP2180 PE-60 TISP2125F3 TISP2150F3 TISP2180F3 2125F3
Text: TISP2125F3, TISP2150F3, TISP2180F3 DUAL SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS Copyright 1997, Power Innovations Limited, UK MARCH 1994 - REVISED SEPTEMBER 1997 TELECOMMUNICATION SYSTEM SECONDARY PROTECTION ● Ion-Implanted Breakdown Region Precise and Stable Voltage
|
Original
|
PDF
|
TISP2125F3,
TISP2150F3,
TISP2180F3
2125F3
2150F3
2180F3
2180f3
2180F
TISP2180
PE-60
TISP2125F3
TISP2150F3
TISP2180F3
2125F3
|
BIT3112
Abstract: DMI FUSE
Text: Intel Xeon® Processor L3406 Datasheet – Volume 2 March 2010 Document Number: 323055-001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
|
Original
|
PDF
|
L3406
L3406
BIT3112
DMI FUSE
|
ME 4946
Abstract: No abstract text available
Text: ISL5216 TM Data Sheet February 2002 Four-Channel Programmable Digital DownConverter FN6013.1 Features • Up to 95MSPS Input The ISL5216 Quad Programmable Digital DownConverter QPDC is designed for high dynamic range applications such as cellular basestations where multiple channel
|
Original
|
PDF
|
ISL5216
FN6013
ISL5216
16-bit
14-bit
ME 4946
|
circuit diagram wireless spy camera
Abstract: interfacing 8051 with 300 GSM Modem datasheet PIC Microcontroller GSM Modem cash box guard project with procedure pmb 4220 interfacing 8051 with GSM Modem Siemens pmb 4220 pbc 05 ericsson Marking Code SMD databook gsm coding in c for 8051 microcontroller
Text: Contents Page Introduction . Quality Assurance . Page 3 Package Information 4 Summary of Types in Alphanumerical Order Mobile Communication ICs . 208 . 209 .
|
Original
|
PDF
|
D-81671
circuit diagram wireless spy camera
interfacing 8051 with 300 GSM Modem datasheet
PIC Microcontroller GSM Modem
cash box guard project with procedure
pmb 4220
interfacing 8051 with GSM Modem
Siemens pmb 4220
pbc 05 ericsson
Marking Code SMD databook
gsm coding in c for 8051 microcontroller
|
structure interpolation CIC Filter
Abstract: SDXC F804 HSP50216 HSP50216KI HSP50216KIZ SD2C 00A140
Text: HSP50216 TM Data Sheet July 31, 2006 Four-Channel Programmable Digital DownConverter Features • Up to 70MSPS Input The HSP50216 Quad Programmable Digital DownConverter QPDC is designed for high dynamic range applications such as cellular basestations where multiple channel
|
Original
|
PDF
|
HSP50216
FN4557
70MSPS
HSP50216
16-Bit
32-Bit
structure interpolation CIC Filter
SDXC
F804
HSP50216KI
HSP50216KIZ
SD2C
00A140
|
DIP20
Abstract: M5913 M5913B1
Text: M5913 COMBINED SINGLE CHIP PCM CODEC AND FILTER SYNCHRONOUS CLOCKS ONLY AT&T D3/D4 AND CCITT COMPATIBLE TWO TIMING MODES: FIXED DATA RATE MODE 1.536MHz, 1.544MHz, 2.048MHz VARIABLE DATA MODE: 64KHz - 4.096MHz PIN SELECTABLE µ-LAW OR A-LAW OPERATION NO EXTERNAL COMPONENTS FOR SAMPLE-AND-HOLD AND AUTO ZERO FUNCTIONS
|
Original
|
PDF
|
M5913
536MHz,
544MHz,
048MHz
64KHz
096MHz
M5913
M5913-Digital
M5913B1
DIP20
M5913B1
|
transistor EN 13003 A
Abstract: sw 13003 transistor EN 13003 X 13003 AL 13003 70 13003 complement 47-16 n2 LG 631 IC 13003 application notes ISL5416
Text: ISL5416 Data Sheet February 2003 Four-Channel Wideband Programmable DownConverter FN6006.2 Features • Up to 95MSPS Input The ISL5416 Four-Channel Wideband Programmable Digital DownConverter WPDC is designed for high dynamic range applications such as cellular basestations where the
|
Original
|
PDF
|
ISL5416
FN6006
95MSPS
ISL5416
16-bit
17-bit
32-Bit
110dB
20-bit
transistor EN 13003 A
sw 13003
transistor EN 13003
X 13003
AL 13003 70
13003 complement
47-16 n2
LG 631 IC
13003 application notes
|
ana 658 solar charge
Abstract: RD2004 for 4120 40A 14VDC relay pico fuse color code varistor 20sp Lucent SLC 96 cabinet MDM cooper bussmann semiconductor fuse catalogue MDQ 100a 600v bridge rectifier GBA 616
Text: Bussmann electrical full line catalog Leadership in Circuit Protection Introducing Bussmann by Eaton The protection you rely on. For more, visit Bussmann.com Leadership in Circuit Protection. The only company that can provide a complete circuit protection solution for all applications.
|
Original
|
PDF
|
|
|
|
Untitled
Abstract: No abstract text available
Text: 181-00249 Home Events Careers How To Buy Contact Search Products Cable Ties Cable Ties with Fasteners Cable Tie Tools Clamps and Clips Industries Resources News About Us 181-00249 Solid Wall Wiring Duct, 2" X 5", Non-Adhesive, PVC, White, 30ft/Carton Order Samples
|
Original
|
PDF
|
30ft/Carton
TS16949,
|
Untitled
Abstract: No abstract text available
Text: NOV 3 t Î99I ! Preliminary Advanced Micro Devices Am2075 ISDN Digital Exchange Controller IDEC DISTINCTIVE CHARACTERISTICS • Four independent HDLC channels ■ 64-byte FIFO storage per channel and Programmable time slots and channel data rates (up to 4 Mb/s)
|
OCR Scan
|
PDF
|
Am2075
64-byte
7/11/S0
|
29C14
Abstract: No abstract text available
Text: in t e T o o r i í AND 9QP1d CHMOS COMBINED SINGLE-CHIP PCM CODEC AND FILTER AT&T D3/D4 and CCITT Compatible 29C14 Asynchronous Clocks, 8th Bit Signaling, Loop Back Test Capability 3 Low-Power Modes — 3.5 mW Typical Power Down — 3.5 mW Typical Standby
|
OCR Scan
|
PDF
|
29C14
29C13
28-Pin
29C14
|
BMS404
Abstract: No abstract text available
Text: S IEM EN S ISDN D-Channel Exchange Controller IDEC PEB 2075 CM OS 1C 1 • • • • • • • • • • • • • Features Four independent HDLC channels 64-byte FIFO storage per channel and direction Handling of basic HDLC functions flag detection/generation
|
OCR Scan
|
PDF
|
64-byte
P-DIP-28
2075-N
P-LCC-44
flB35bD5
D07Dbfiti
BMS404
|
PLCC-44 SMD
Abstract: No abstract text available
Text: ISDN D-Channel Exchange Controller IDEC" PEB 2075 G eneral D escription With the IOM-2 interface, designers have more flexibility with respect to handling of D-channel information. Layer-1 transceivers are connected over the IOM-2 interface directly to either the PEB 2055 (EPIC-1) or the PEB 2054 (EPIC-S).
|
OCR Scan
|
PDF
|
2075-N
2075-P
2075-N
P-LCC-44-'
P-DIP-28-1
64-byte
PLCC-44 SMD
|
ITA03537
Abstract: ITD03534 Q67100-H6189 siemens G75 A 80 ACO3
Text: S IEM EN S ISDN D-Channel Exchange Controller IDEC PEB 2075 CM OS IC 1 • • • • • • • • • • • • • Features Four independent HDLC channels 64-byte FIFO storage per channel and direction Handling of basic HDLC functions flag detection/generation
|
OCR Scan
|
PDF
|
64-byte
P-DIP-28
P-LCC-44
flB35b05
ITA03537
ITD03534
Q67100-H6189
siemens G75 A 80
ACO3
|
HIGHWAY 08 20 PIN IC PIN DIAGRAM
Abstract: No abstract text available
Text: ^ IL O ÌM O IM « 2916 AND 2917 16-PIN SINGLE CHIP PCM CODEC AND FILTER • 2916/u-Law, 2.048 MHz Master Clock ■ 2917 A-Law, 2.048 MHz Master Clock ■ New 16-Pin Package for Higher Linecard Density ■ Fully Differential Architecture Enhances Noise Immunity
|
OCR Scan
|
PDF
|
16-PIN
2916/u-Law,
32-Channel
--140mW
HIGHWAY 08 20 PIN IC PIN DIAGRAM
|
sinusoidal
Abstract: POWER SUPPLY 2916 fxs interface integrated circuit
Text: in t j, 2916/2917 HMOS COMBINED SINGLE CHIP PCM CODEC AND FILTER 2916 /x-Law, 2.048 MHz Master Clock 2917 A-Law, 2.048 MHz Master Clock New 16-Pin Package for Higher Linecard Density AT&T D3/D4 and CCITT Compatible Variable Timing Mode for Flexible Digital Interface: Supports Data Rates
|
OCR Scan
|
PDF
|
16-Pin
32-Channel
sinusoidal
POWER SUPPLY 2916
fxs interface integrated circuit
|
Untitled
Abstract: No abstract text available
Text: intJ. 2916/2917 HMOS COMBINED SINGLE CHIP PCM CODEC AND FILTER 2916 ft-Law, 2.048 MHz Master Clock Fixed Timing Mode for Standard 32-Channel Systems: 2.048 MHz Master Clock 2917 A-Law, 2.048 MHz Master Clock New 16-Pin Package for Higher Linecard Density Low Power HMOS-E Technology
|
OCR Scan
|
PDF
|
32-Channel
16-Pin
|
Untitled
Abstract: No abstract text available
Text: _ 8 _ File No. ~— 4 32 r SHEET ILL SPECIFICATION /tN /t\ ./ tv /"hs \J7 /t\ /"N /"K tj/ \f7 A io o o o *— -H O lO -H o o /tN /t\ vj/ /t\ /TV /*N /"N /tN Vj7 \$s \f7 /t\ /fN /*N fN Vj7 /"N / t \ vj/ /fN /"hs /*N fN Vf7 \J7 /"N Current Rating: 2.0Am p
|
OCR Scan
|
PDF
|
UL94V-0
|
