Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    PLL10 Search Results

    SF Impression Pixel

    PLL10 Price and Stock

    Panduit Corp PLL-10-PO-5

    LABEL LSR POLYFN WHT 1.00 X .75"
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey PLL-10-PO-5 Bulk
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 -
    		Buy Now
    Onlinecomponents.com PLL-10-PO-5
    • 1 $0
    • 10 $0
    • 100 $0
    • 1000 $0
    • 10000 $0
    		Buy Now

    Panduit Corp PLL-10-Y2-2.5

    LABEL LSR POLY WHT .30 X .25"
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey PLL-10-Y2-2.5 Bulk
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 -
    		Buy Now
    Mouser Electronics PLL-10-Y2-2.5
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 $0.116
    		Get Quote
    Onlinecomponents.com PLL-10-Y2-2.5
    • 1 $0
    • 10 $0
    • 100 $0
    • 1000 $0
    • 10000 $0
    		Buy Now

    PLL10 Datasheets (84)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    PLL1000A Z-Communications PHASE LOCKED LOOP Original PDF
    PLL1000A-LF Z-Communications IC PLL SNGL 988 TO 1028MHZ 5V Original PDF
    PLL102-01TC PhaseLink Low Voltage PLL Clock Drivers Original PDF
    PLL102-01TI PhaseLink Low Voltage PLL Clock Drivers Original PDF
    PLL102-01TM PhaseLink Low Voltage PLL Clock Drivers Original PDF
    PLL102-03 PhaseLink Low Skew Output Buffer Original PDF
    PLL102-03SC PhaseLink Low Skew Output Buffer Original PDF
    PLL102-03SCL PhaseLink Low Skew Output Buffer Original PDF
    PLL102-03SCL-R PhaseLink Low Skew Output Buffer Original PDF
    PLL102-03SC-R PhaseLink Low Skew Output Buffer Original PDF
    PLL102-04 PhaseLink Low Skew Output Buffer Original PDF
    PLL102-04SC PhaseLink Low Skew Output Buffer Original PDF
    PLL102-04SCL PhaseLink Low Skew Output Buffer Original PDF
    PLL102-04SCL-R PhaseLink Low Skew Output Buffer Original PDF
    PLL102-04SC-R PhaseLink Low Skew Output Buffer Original PDF
    PLL102-05 PhaseLink Low Skew Output Buffer Original PDF
    PLL102-05SC PhaseLink Low Skew Output Buffer Original PDF
    PLL102-05SCL PhaseLink Low Skew Output Buffer Original PDF
    PLL102-05SCL-R PhaseLink Low Skew Output Buffer Original PDF
    PLL102-05SC-R PhaseLink Low Skew Output Buffer Original PDF

    PLL10 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    400ps a2

    Abstract: PLL102-108
    Text: PLL102-108 Programmable DDR Zero Delay Clock Driver FEATURES • • • • • • PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. Distributes one clock Input to one bank of ten differential outputs. Track spread spectrum clocking for EMI reduction.


    Original     		PDF PLL102-108 266Mhz. 100ps. 48-Pin 300mil 400ps a2 PLL102-108

    PLL103-11

    Abstract: No abstract text available
    Text: PLL103-11 Low Skew Buffers FEATURES • • • Generates 13 copies of High-speed clock inputs. Supports up to three SDRAM DIMMS synchronous clocks. Supports 2-wire I2C serial bus interface with readback. 50% duty cycle with low jitter. Less than 5ns delay.


    Original     		PDF PLL103-11 28-pin 300mil SDRAM11 SDRAM10 PLL103-11

    Untitled

    Abstract: No abstract text available
    Text: PLL1070A 9939 Via Pasar • San Diego, CA 92126 TEL 858 621-2700 FAX (858) 621-2722 PHASE LOCKED LOOP Rev A PHASE NOISE (1 Hz BW, typical) FEATURES • Frequency Range: 1055 - 1105 MHz • Step Size: 30 KHz • PLL - Style Package APPLICATIONS • Basestations


    Original     		PDF PLL1070A AN-200 AN-201 AN-202

    PLL103-53

    Abstract: DDR6
    Text: Preliminary PLL103-53 DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS FEATURES • • • Generates 30-output buffers from one input. Supports up to 4 DDR DIMMS or 3 SDR DIMMS and 2 DDR DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback.


    Original     		PDF PLL103-53 30-output 266MHz SDRAM10 SDRAM11 DDR11T DDR11C DDR10T DDR10C PLL103-53 DDR6

    PLL103-01

    Abstract: No abstract text available
    Text: PLL103-01 Low Skew Buffers FEATURES • • • Generate 18 copies of High-speed clock inputs. Supports up to four SDRAM DIMMS synchronous clocks. Supports 2-wire I2C serial bus interface with readback. 50% duty cycle with low jitter. Less than 5ns delay.


    Original     		PDF PLL103-01 48-pin SDRAM15 SDRAM14 SDRAM13 SDRAM11 SDRAM10 PLL103-01

    PLL103-06

    Abstract: PLL202-04
    Text: Preliminary PLL103-06 DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS FEATURES • • • Generates 12-output buffers from one input. Supports up to 2 DDR DIMMS or 3 SDRAM DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback. Less than 5ns delay.


    Original     		PDF PLL103-06 12-output 266MHz SDRAM10 SDRAM11 PLL103-06 PLL202-04

    PLL103-05

    Abstract: No abstract text available
    Text: Preliminary PLL103-05 1-to-5 Clock Distribution Buffer FEATURES 5 outputs identical to FIN. Low skew < 250 ps between outputs . Input / Output frequency range 0 – 160 MHz 25mA drive capability at TTL levels. 70mA drive capability at CMOS levels. 3.3V operation.


    Original     		PDF PLL103-05 150mil PLL103-05

    PLL103-04

    Abstract: No abstract text available
    Text: Preliminary PLL103-04 1-to-4 Clock Distribution Buffer FEATURES • • 4 outputs identical to FIN. Low skew < 250 ps between outputs . Input / Output frequency range 0 – 160 MHz 25mA drive capability at TTL levels. 70mA drive capability at CMOS levels.


    Original     		PDF PLL103-04 150mil PLL103-04

    ddr5

    Abstract: PLL103-02 PLL202-04
    Text: PLL103-02 DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS FEATURES • • • Generates 24 output buffer from one input. Supports up to four DDR DIMMS or 2 SDRAM DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback. Less than 5ns delay.


    Original     		PDF PLL103-02 266MHz DDR11T DDR11C DDR10T DDR10C ddr5 PLL103-02 PLL202-04

    AN-200

    Abstract: AN-201 AN-202 PLL1045A OSC-40MHZ
    Text: PLL1045A 9939 Via Pasar • San Diego, CA 92126 TEL 858 621-2700 FAX (858) 621-2722 PHASE LOCKED LOOP Rev A1 PHASE NOISE (1 Hz BW, typical) FEATURES • Frequency Range: 1020 - 1070 MHz • Step Size: 30 KHz • PLL - Style Package APPLICATIONS • Basestations


    Original     		PDF PLL1045A AN-201 AN-202 AN-200 AN-201 AN-202 PLL1045A OSC-40MHZ

    1055

    Abstract: AN-200 AN-201 AN-202 PLL1070A
    Text: PLL1070A 9939 Via Pasar • San Diego, CA 92126 TEL 858 621-2700 FAX (858) 621-2722 PHASE LOCKED LOOP Rev A PHASE NOISE (1 Hz BW, typical) FEATURES • Frequency Range: 1055 - 1105 MHz • Step Size: 30 KHz • PLL - Style Package APPLICATIONS • Basestations


    Original     		PDF PLL1070A AN-201 AN-202 1055 AN-200 AN-201 AN-202 PLL1070A

    m16811

    Abstract: u48 PMU ICS952501 BT135 1001 dl pwm quanta T210P 12Bst MAX8863SEUK T quanta computer
    Text: 1 2 3 4 5 6 CPUCLK+ CPUCLK- Power - Source Control HCLK+ HCLK- CPU CORE Power PAGE 41. PAGE 38. PCLK_MPCI ICS952501 (PLL202-108) PCLK_1394 MCLK PCLK_591 A PCLK_SB CLOCKS buffer (ICS93735) (PLL102-108) GCLK PAGE 40. PCI BUS Routing Table =


    Original     		PDF ICS952501) PLL202-108) M1681 M1563 USB20 ICS93735) PLL102-108) ISL6207 1U25V m16811 u48 PMU ICS952501 BT135 1001 dl pwm quanta T210P 12Bst MAX8863SEUK T quanta computer

    ICS553

    Abstract: P102 PLL102-04 PLL102-15 buffer DT2
    Text: PLL102-15 Low Skew Output Buffer FEATURES • • • • • • • Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spec trum modulation on reference clock to pass to the outputs up to 33kHz SST modulation . Zero input - output delay.


    Original     		PDF PLL102-15 60MHz. 33kHz 150mil 100kHz 33kHz. 25-75MHz" 25-60MHz" 67MHz" ICS553 P102 PLL102-04 PLL102-15 buffer DT2

    ddr4t

    Abstract: PLL103-02 PLL103-02XC PLL103-02XC-R
    Text: PLL103-02 DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS FEATURES • • • • • • • • • PIN CONFIGURATION Generates 24 output buffers from one input. Supports up to four DDR DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback.


    Original     		PDF PLL103-02 266MHz DDR11T DDR11C DDR10T DDR10C ddr4t PLL103-02 PLL103-02XC PLL103-02XC-R

    PLL102-04SCL-R

    Abstract: P102-04SC PLL102-04 PLL102-04SC PLL102-04SCL PLL102-04SC-R
    Text: PLL102-04 Low Skew Output Buffer FEATURES • • Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs up to 100kHz SST modulation . Zero input - output delay. Less than 700 ps device - device skew.


    Original     		PDF PLL102-04 120MHz. 100kHz 150mil PLL102-04 PLL102-04SCL-R P102-04SC PLL102-04SC PLL102-04SCL PLL102-04SC-R

    P102-05SC

    Abstract: PLL102-05 PLL102-05SC PLL102-05SCL PLL102-05SCL-R PLL102-05SC-R
    Text: PLL102-05 Low Skew Output Buffer FEATURES • • • • • • • Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs up to 100kHz SST modulation . Zero input - output delay.


    Original     		PDF PLL102-05 60MHz. 100kHz 150mil P102-05SC PLL102-05 PLL102-05SC PLL102-05SCL PLL102-05SCL-R PLL102-05SC-R

    MPC932P

    Abstract: No abstract text available
    Text: PLL102-01 Low Voltage PLL Clock Drivers Q5 VCCO VSSO Q4 VCCO Q3 25 24 23 22 21 20 19 18 17 16 VCCQ0 26 15 QFB Q0 27 14 VCCO_QFB VSSO 28 SD1:2 29 SD0 VSS0_QFB 13 FB_IN 12 SD3 30 11 SD4 MODE 31 10 VCCA 32 9 SD5 VSSA 1 2 3 4 5 6 7 8 FBSEL0 FBSEL1 MR/OE COM_SD


    Original     		PDF PLL102-01 133MHz. MPC932P. MPC932P

    phase locked loop

    Abstract: AN-201 AN-200 AN-202 PLL1000A
    Text: PLL1000A 9939 Via Pasar • San Diego, CA 92126 TEL 858 621-2700 FAX (858) 621-2722 PHASE LOCKED LOOP Rev A PHASE NOISE (1 Hz BW, typical) FEATURES • Frequency Range: 988 - 1028 MHz • Step Size: 1000 KHz • PLL - Style Package APPLICATIONS • Basestations


    Original     		PDF PLL1000A AN-107 AN-200 AN-201 AN-202 phase locked loop AN-201 AN-200 AN-202 PLL1000A

    PLL102-109

    Abstract: No abstract text available
    Text: Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver FEATURES • • • • • • PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. Distributes one clock Input to one bank of six differential outputs. Track spread spectrum clocking for EMI reduction.


    Original     		PDF PLL102-109 266Mhz. 100ps. PLL102-109

    PLL103-07

    Abstract: PLL202-04
    Text: Preliminary PLL103-07 2 DIMM DDR Fanout Buffer FEATURES Generates 12-output buffers from one input. Supports VIA Pro266 DDR chipset. Supports up to 2 DDR DIMMS. Supports up to 400MHz DDR, SDRAMS. One additional output for feedback. 6 differential clock distribution.


    Original     		PDF PLL103-07 12-output Pro266 400MHz 28-pin PLL103-07 PLL202-04

    ddr5

    Abstract: PLL103-02 PLL202-04 ddr-7-t
    Text: PLL103-02 Rev.D DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS FEATURES Generates 24 output buffer from one input. Supports up to four DDR DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback. Less than 5ns delay. Skew between any outputs is less than 100 ps.


    Original     		PDF PLL103-02 266MHz DDR11T DDR11C DDR10T DDR10C ddr5 PLL202-04 ddr-7-t

    PLL103-03

    Abstract: PLL202-04
    Text: Preliminary PLL103-03 DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS FEATURES • • • Generates 24-output buffers from one input. Supports up to 4 DDR DIMMS or 3 SDR DIMMS and 2 DDR DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback.


    Original     		PDF PLL103-03 24-output 266MHz SDRAM10 DDR11T SDRAM11 DDR11C DDR10T DDR10C PLL103-03 PLL202-04

    P102-10SC

    Abstract: PLL102-10 PLL102-10SC PLL102-10SC-R
    Text: PLL102-10 Low Skew Output Buffer FEATURES • • Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to outputs. Zero input - output delay. Less than 700 ps device - device skew. Less than 250 ps skew between outputs.


    Original     		PDF PLL102-10 120MHz. PLL102-10 P102-10SC PLL102-10SC PLL102-10SC-R

    P102-03SC

    Abstract: PLL102-03 PLL102-03SC PLL102-03SCL PLL102-03SCL-R PLL102-03SC-R
    Text: PLL102-03 Low Skew Output Buffer FEATURES • • Frequency range 75 ~ 180MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs up to 100kHz SST modulation . Zero input - output delay. Less than 700 ps device - device skew.


    Original     		PDF PLL102-03 180MHz. 100kHz 150mil PLL102-03 P102-03SC PLL102-03SC PLL102-03SCL PLL102-03SCL-R PLL102-03SC-R