Untitled
Abstract: No abstract text available
Text: IDT - Integrated Device Technology Page 1 of 2 Integrated Device Technology Products | Applications Clock / Timing Devices | Search PC Motherboard Clocks 9LPRS397EKLFT | Support The Analog and Digital Company | Investor | About IDT Mobile > 9LPRS397 > 9LPRS397EKLFT
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9LPRS397EKLFT
9LPRS397
A0903-04
A0808-02
VFQFP-N-64
VFQFP-N-72
TB0807-01
VFQFP-N-68,
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NLG72
Abstract: gps 1pps holdover GR-253-CORE
Text: Dual Synchronous Ethernet Line Card PLL FEATURES • HIGHLIGHTS • Dual PLL chip: • Provides clocks for ITU-T G.8261/G.8262 Synchronous Ethernet SyncE • Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-4) jitter generation requirements • Provides clocks for Cellular and WLL base-station (GSM and 3G
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8261/G
GR-253-CORE
OC-12)
NLG72
gps 1pps holdover
GR-253-CORE
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history of automatic phase selector
Abstract: IDT82V3399 NLG72 82V3399B gps 1pps holdover 1pps IEEE1588 NLG7282V3399B
Text: SYNCHRONOUS ETHERNET WAN PLL and Clock Generation for IEEE-1588 FEATURES • HIGHLIGHTS • Single chip PLL: • Features 0.5 mHz to 560 Hz bandwidth • Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet SyncE • Exceeds GR-253-CORE (OC-192) and ITU-T G.813 (STM-64)
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Original
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PDF
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IEEE-1588
8261/G
GR-253-CORE
OC-192)
STM-64)
IEEE-1588
history of automatic phase selector
IDT82V3399
NLG72
82V3399B
gps 1pps holdover
1pps
IEEE1588
NLG7282V3399B
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Untitled
Abstract: No abstract text available
Text: SYNCHRONOUS ETHERNET WAN PLL and Clock Generation for IEEE-1588 • FEAT U RES HIGHLIGHTS • Single chip PLL: • Features 0.5 mHz to 560 Hz bandwidth • Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet SyncE • Exceeds GR-253-CORE (OC-192) and ITU-T G.813 (STM-64)
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Original
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PDF
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IEEE-1588
8261/G
GR-253-CORE
OC-192)
STM-64)
IEEE-1588
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Untitled
Abstract: No abstract text available
Text: Dual Synchronous Ethernet Line Card PLL FEATURES • • HIGHLIGHTS • Dual PLL chip: • Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet SyncE • Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-4) jitter generation requirements • Provides node clocks for Cellular and WLL base-station (GSM
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PDF
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8261/G
GR-253-CORE
OC-12)
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CK410
Abstract: NLG72 VFQFPN DB1900GS
Text: Search Entire Site Contact IDT | Investors | Press Document Search | Package Search | Parametric Search | Cross Reference Search | Green & RoHS | Calculators | Thermal Data | Reliability & Quality | Military Home > Products > Clock / Timing Devices > PC-Notebook-Server Clocks > PCIe/HCSL Buffers and Generators > 9FG1900-1 >
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9FG1900-1
9FG1900AK-1LF
9FG1900AK1LF
9FG1900-1
ICS9FG1900-1
DB1900GS
VFQFP-N-72
A0701-02R1
CK410
NLG72
VFQFPN
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Untitled
Abstract: No abstract text available
Text: Dual Synchronous Ethernet Line Card PLL • FEAT U RES HIGHLIGHTS • Dual PLL chip: • Provides clocks for ITU-T G.8261/G.8262 Synchronous Ethernet SyncE • Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-4) jitter generation requirements • Provides clocks for Cellular and WLL base-station (GSM and 3G
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Original
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PDF
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8261/G
GR-253-CORE
OC-12)
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tms 1944
Abstract: 741 Ic1
Text: SYNCHRONOUS ETHERNET WAN PLL and Clock Generation for IEEE-1588 FEATURES • HIGHLIGHTS • Single PLL chip: • Features 0.5 mHz to 560 Hz bandwidth • Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet SyncE • Exceeds GR-253-CORE (OC-192) and ITU-T G.813 (STM-64)
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Original
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PDF
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IEEE-1588
8261/G
GR-253-CORE
OC-192)
STM-64)
IEEE-1588
tms 1944
741 Ic1
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