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    LOGIC DESCRIPTION OF 74LS138 Search Results

    LOGIC DESCRIPTION OF 74LS138 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74HC4053FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SPDT(1:2)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    74HC4051FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SP8T(1:8)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    DCL541A01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: Low / Input disable Visit Toshiba Electronic Devices & Storage Corporation
    DCL542H01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=2:2) / Default Output Logic: High / Output enable Visit Toshiba Electronic Devices & Storage Corporation
    DCL541B01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: High / Input disable Visit Toshiba Electronic Devices & Storage Corporation

    LOGIC DESCRIPTION OF 74LS138 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74LS138

    Abstract: 74LS138 3 to 8 decoder Pin 74LS138 pin diagram ls138 74LS138 3 to 8 decoder notes pin for 74LS138 TTL 74ls138 Truth table of 1 to 16 demultiplexer of 74LS138 3 to 8 decoder 74ls138 truth table
    Text: SN54/74LS138 1-OF-8 DECODER/ DEMULTIPLEXER The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of-8 Decoder / Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32


    Original     		PDF SN54/74LS138 74LS138 1-of-24 LS138 1-of-32 LS138s 74LS138 3 to 8 decoder Pin 74LS138 pin diagram 74LS138 3 to 8 decoder notes pin for 74LS138 TTL 74ls138 Truth table of 1 to 16 demultiplexer of 74LS138 3 to 8 decoder 74ls138 truth table

    block diagram of 74LS138 3 to 8 decoder

    Abstract: 74LS138 3 to 8 decoder notes block diagram of 74LS138 1 line to 16 line MM74HCT138N mm54hct138/mm74hct138 54LS138 74HCT 74LS138 C1995 MM54HCT138
    Text: MM54HCT138 MM74HCT138 3-to-8 Line Decoder General Description the 54LS138 74LS138 All inputs are protected from damage due to static discharge by diodes to VCC and ground MM54HCT MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS


    Original     		PDF MM54HCT138 MM74HCT138 54LS138 74LS138 MM54HCT MM74HCT MM74HCT138 block diagram of 74LS138 3 to 8 decoder 74LS138 3 to 8 decoder notes block diagram of 74LS138 1 line to 16 line MM74HCT138N mm54hct138/mm74hct138 74HCT C1995

    74LS138 3 to 8 decoder notes

    Abstract: 74LS138 DATASHEET motorola 74ls138 TTL 74ls138 FUNCTIONAL APPLICATION OF 74LS138 74LS138 data sheet 74LS138 1 to 8 decoder notes 74LS138 application note 74ls138 LS138 Motorola
    Text: SN54/74LS138 1-OF-8 DECODER/ DEMULTIPLEXER The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of-8 Decoder / Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32


    Original     		PDF SN54/74LS138 74LS138 1-of-24 LS138 1-of-32 LS138s 74LS138 3 to 8 decoder notes 74LS138 DATASHEET motorola 74ls138 TTL 74ls138 FUNCTIONAL APPLICATION OF 74LS138 74LS138 data sheet 74LS138 1 to 8 decoder notes 74LS138 application note LS138 Motorola

    motorola 6802

    Abstract: intel 8748 microprocessor 6802 processor motorola M027 Interfacing the HCTL-20XX Encoder interface with HCTL-2016 M019 intel 8748 motorola intel 6802 shaft encoder HCTL-20XX INSTRUCTION SET motorola 6802
    Text: HCTL-2000, HCTL-2016, HCTL-2020 Quadrature Decoder/Counter Interface ICs Data Sheet Description Features The HCTL-2000, 2016, 2020 are CMOS ICs that perform the quadrature decoder, counter, and bus interface function. The HCTL-20XX family is designed to improve system performance in digital closed loop motion control systems


    Original     		PDF HCTL-2000, HCTL-2016, HCTL-2020 HCTL-20XX HCTL-2020 16-bit MC68HCII motorola 6802 intel 8748 microprocessor 6802 processor motorola M027 Interfacing the HCTL-20XX Encoder interface with HCTL-2016 M019 intel 8748 motorola intel 6802 shaft encoder HCTL-20XX INSTRUCTION SET motorola 6802

    datasheet 6802 processor motorola

    Abstract: HCTL-2020 HCTL-2020 circuit m027 HCTL-2000 HCTL-2016 HCTL2020 HCTL-20XX 74ls138 intel 8748
    Text: H Quadrature Decoder/Counter Interface ICs Technical Data HCTL-2000 HCTL-2016 HCTL-2020 Features • Interfaces Encoder to Microprocessor • 14 MHz Clock Operation • Full 4X Decode • High Noise Immunity: Schmitt Trigger Inputs Digital Noise Filter • 12 or 16-Bit Binary Up/


    Original     		PDF HCTL-2000 HCTL-2016 HCTL-2020 16-Bit HCTL-2000, HCTL-20XX HCTL2020 HCTL-2020 16-bit datasheet 6802 processor motorola HCTL-2020 circuit m027 HCTL-2000 HCTL-2016 HCTL-20XX 74ls138 intel 8748

    datasheet 6802 processor motorola

    Abstract: shaft encoder HCTL-20XX intel 8748 microprocessor M027 Interfacing the HCTL-20XX 6802 processor motorola INSTRUCTION SET motorola 6802 m027 HCTL-2020 HCTL-20XX Quadrature Decoder Interface ICs
    Text: HCTL-2000 Quadrature Decoder/Counter Interface ICs Data Sheet HCTL-2000, HCTL-2016, HCTL-2020 Description The HCTL-2000, 2016, 2020 are CMOS ICs that perform the quadrature decoder, counter, and bus interface function. The HCTL-20XX family is designed to improve system performance in digital closed loop


    Original     		PDF HCTL-2000 HCTL-2000, HCTL-2016, HCTL-2020 HCTL-20XX HCTL-20XX HCTL2020 HCTL-2020 datasheet 6802 processor motorola shaft encoder HCTL-20XX intel 8748 microprocessor M027 Interfacing the HCTL-20XX 6802 processor motorola INSTRUCTION SET motorola 6802 m027 Quadrature Decoder Interface ICs

    block diagram of 74LS138 3 to 8 decoder

    Abstract: 6802 processor motorola intel 8748 HCTL-2016 circuit datasheet 6802 processor motorola HCTL-2020 M027 Interfacing the HCTL-20XX HCTL-1101 Application 8051 quadrature decoder 4X HCTL-2000
    Text: H Quadrature Decoder/Counter Interface ICs Technical Data HCTL-2000 HCTL-2016 HCTL-2020 Features • Interfaces Encoder to Microprocessor • 14 MHz Clock Operation • Full 4X Decode • High Noise Immunity: Schmitt Trigger Inputs Digital Noise Filter • 12 or 16-Bit Binary Up/


    Original     		PDF HCTL-2000 HCTL-2016 HCTL-2020 16-Bit HCTL-2000, HCTL-20XX HCTL2020 HCTL-2020 16-bit block diagram of 74LS138 3 to 8 decoder 6802 processor motorola intel 8748 HCTL-2016 circuit datasheet 6802 processor motorola M027 Interfacing the HCTL-20XX HCTL-1101 Application 8051 quadrature decoder 4X HCTL-2000

    HCTL-2000

    Abstract: block diagram of 74LS138 3 to 8 decoder datasheet 6802 processor motorola 6802 processor motorola HCTL-20XX HCTL-2020 circuit intel 8748 M019 HCTL-1101 Application 8051 74LS697
    Text: Quadrature Decoder/Counter Interface ICs Technical Data HCTL-2000 HCTL-2016 HCTL-2020 Features • Interfaces Encoder to Microprocessor • 14 MHz Clock Operation • Full 4X Decode • High Noise Immunity: Schmitt Trigger Inputs Digital Noise Filter • 12 or 16-Bit Binary Up/


    Original     		PDF HCTL-2000 HCTL-2016 HCTL-2020 16-Bit HCTL-2000, HCTL-20XX HCTL2020 HCTL-2020 16-bit HCTL-2000 block diagram of 74LS138 3 to 8 decoder datasheet 6802 processor motorola 6802 processor motorola HCTL-20XX HCTL-2020 circuit intel 8748 M019 HCTL-1101 Application 8051 74LS697

    datasheet 6802 processor motorola

    Abstract: 3 to 8 line decoder using 8051 intel 8748 motorola intel 6802 HCTL-20XX 74LS697 6802 processor motorola 74LS138 decoder motorola 6802 m027
    Text: Quadrature Decoder/Counter Interface ICs Technical Data HCTL-2000 HCTL-2016 HCTL-2020 Features • Interfaces Encoder to Microprocessor • 14 MHz Clock Operation • Full 4X Decode • High Noise Immunity: Schmitt Trigger Inputs Digital Noise Filter • 12 or 16-Bit Binary Up/


    Original     		PDF HCTL-2000 HCTL-2016 HCTL-2020 16-Bit HCTL-2000, HCTL-20XX HCTL2020 HCTL-2020 16-bit datasheet 6802 processor motorola 3 to 8 line decoder using 8051 intel 8748 motorola intel 6802 HCTL-20XX 74LS697 6802 processor motorola 74LS138 decoder motorola 6802 m027

    M027 Interfacing the HCTL-20XX

    Abstract: intel 8748 ic 74ls138 pdf datasheet 74LS138 3 to 8 decoder notes Quadrature Decoder Interface ICs datasheet 6802 processor motorola block diagram of 74LS138 3 to 8 decoder block diagram of 74LS138 1 line to 16 line frequency counter using 8051 74LS138 3 to 8 decoder Pin Description
    Text: Quadrature Decoder/Counter Interface ICs Technical Data HCTL-2000 HCTL-2016 HCTL-2020 Features • Interfaces Encoder to Microprocessor • 14 MHz Clock Operation • Full 4X Decode • High Noise Immunity: Schmitt Trigger Inputs Digital Noise Filter • 12 or 16-Bit Binary Up/


    Original     		PDF HCTL-2000 HCTL-2016 HCTL-2020 16-Bit HCTL-2020 16-bit MC68HCII 5965-5894E M027 Interfacing the HCTL-20XX intel 8748 ic 74ls138 pdf datasheet 74LS138 3 to 8 decoder notes Quadrature Decoder Interface ICs datasheet 6802 processor motorola block diagram of 74LS138 3 to 8 decoder block diagram of 74LS138 1 line to 16 line frequency counter using 8051 74LS138 3 to 8 decoder Pin Description

    25ls2521

    Abstract: 10F305 74ls245 jtag ansley idc ribbon connector beckman j2 EVQ-QS205K ICE-243-S-TG30 74LS04 SIGNETICS Beckman 661 XTB37-B
    Text: CHAPTER 6 HOST COMPUTER CARD/COMMAND CONVERTER SUPPORT INFORMATION 6.1 INTRODUCTION This chapter provides the connector signal descriptions and parts lists for hardware that is required to run with the ADS software. This list includes the host interface cards, host


    Original     		PDF DSP56001RC 25ls2521 10F305 74ls245 jtag ansley idc ribbon connector beckman j2 EVQ-QS205K ICE-243-S-TG30 74LS04 SIGNETICS Beckman 661 XTB37-B

    pin diagram of ic 74ls138

    Abstract: 74LS138 pin configuration ic 74ls138 74LS138 pin diagram 74ls138 function 74LS138 LOGIC OF 74LS138 74LS138 3 to 8 decoder Pin pin for 74LS138 74ls138 3-8
    Text: 74LS138, S138 Signetics Decoders/Demultiplexers 1-Of-8 Decoder/Demultiplexer Product Specification Logic Products FEATURES • Multiple input enable for easy expansion • Ideal for memory chip select decoding • Direct replacement for Intel 3205 74LS138


    OCR Scan     		PDF 74LS138, 74LS138 74S138 N74S13BN, N74LS138N N74LS138D, N74S138D 1N916, 1N3064, 500ns pin diagram of ic 74ls138 74LS138 pin configuration ic 74ls138 74LS138 pin diagram 74ls138 function LOGIC OF 74LS138 74LS138 3 to 8 decoder Pin pin for 74LS138 74ls138 3-8

    LOGIC OF 74LS138

    Abstract: 74LS138 3 to 8 decoder notes 74LS138 pin configuration 74LS138 pin for 74LS138 74LS138 3 to 8 decoder Pin 74LS138 3 to pin configuration
    Text: Signetics 74LS138, S138 Decoders/Demultiplexers 1-Of-8 Decoder/Demultiplexer Product Specification Logic Products FEATURES • Multiple input enable for easy expansion • Ideal for memory chip select decoding • Direct replacement for Intel 3205 TYPICAL PROPAGATION


    OCR Scan     		PDF 74LS138, 74LS138 74S138 N74S138N, N74LS138N N74LS138D, N74S138D 1N916, 1N3064, 500ns LOGIC OF 74LS138 74LS138 3 to 8 decoder notes 74LS138 pin configuration pin for 74LS138 74LS138 3 to 8 decoder Pin 74LS138 3 to pin configuration

    LOGIC OF 74LS138

    Abstract: pin for 74LS138 74LS138 3 to 8 decoder notes 74LS138 74LS138 pins 74l5138 of 74LS138 3 to 8 decoder 74ls138 function TTL 74ls138 74LS138 3 to 8 decoder Pin
    Text: 74LS138, S138 Signetics Decoders/Dem ultiplexers 1-Of-8 D e co d e r/D e m u ltip le xe r Product Specification L o g ic P rod ucts FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for memory chip select decoding


    OCR Scan     		PDF 74LS138, 1-of-32 1N916, 1N3064, 500ns LOGIC OF 74LS138 pin for 74LS138 74LS138 3 to 8 decoder notes 74LS138 74LS138 pins 74l5138 of 74LS138 3 to 8 decoder 74ls138 function TTL 74ls138 74LS138 3 to 8 decoder Pin

    CI 74LS138

    Abstract: 74LS138 pin configuration TTL 74ls138 74ls138 function 74 LS 138 DECODER intel 3205 74ls138 74l5138 of 74LS138 3 to 8 decoder 74LS138 ttl
    Text: Signelics 74LS138, S138 Decoders/Demultiplexers 1 -O f - 8 D e c o d e r /D e m u ltip le x e r Product Specification L o g ic P ro d u c ts FEATURES • Demultiplexing capability • Multiple input enable fo r easy expansion TYPE 74LS138 74S138 • Ideal fo r m em ory chip select


    OCR Scan     		PDF -of-32 1N916, 1N3064, 500ns CI 74LS138 74LS138 pin configuration TTL 74ls138 74ls138 function 74 LS 138 DECODER intel 3205 74ls138 74l5138 of 74LS138 3 to 8 decoder 74LS138 ttl

    74ls138 truth table

    Abstract: 74LS138 74 LS 138 DECODER connection for 74LS138 74LS138 3 to 8 decoder Pin demultiplexer 3 to 8 truth table 74ls138 demultiplexer LS138 LOGIC OF 74LS138 of 74LS138 3 to 8 decoder
    Text: g MOTOROLA SN54/74LS138 1-0F-8 DECODER/ DEMULTIPLEXER The LSTTL/MSI SN54/74LS138 is a high speed 1-of-8 Decoder/ Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel ex­


    OCR Scan     		PDF SN54/74LS138 1-of-24 LS138 1-of-32 LS138s SN54/74LS138 74ls138 truth table 74LS138 74 LS 138 DECODER connection for 74LS138 74LS138 3 to 8 decoder Pin demultiplexer 3 to 8 truth table 74ls138 demultiplexer LOGIC OF 74LS138 of 74LS138 3 to 8 decoder

    and gate 74LS138

    Abstract: SP74HCT138N TTL 74ls138 74LS138 LOGIC OF 74LS138 pin for 74LS138 74LS138 pin configuration SP74HCT138 SP74HCT138J 74LS138 pin
    Text: SPI •jri- SP74HCT138 DECODER/DEMULTIPLEXER PIN CONFIGURATION A FEATURES B ■ Designed for high performance memory decoders in microprocessor systems ■ 3 to 8 line decoders include 3 enable inputs ■ Pin com patible with 74LS138 ■ SPI CM OS technology


    OCR Scan     		PDF SP74HCT138 74LS138 SP74HCT138 74LS138. 20/iA and gate 74LS138 SP74HCT138N TTL 74ls138 74LS138 LOGIC OF 74LS138 pin for 74LS138 74LS138 pin configuration SP74HCT138J 74LS138 pin

    Untitled

    Abstract: No abstract text available
    Text: January 1988 MM54HCT138/MM74HCT138 3-to-8 Line Decoder General Description the 54LS138/74LS138. All inputs are protected from dam­ age due to static discharge by diodes to Vcc and ground. MM54HCT/MM74HCT devices are intended to interface be­ tween TTL and NMOS components and standard CMOS


    OCR Scan     		PDF MM54HCT138/MM74HCT138 54LS138/74LS138. MM54HCT/MM74HCT

    LS139

    Abstract: LS138 LS138-LS139 74LS139 DM74LS139N
    Text: LS138-LS139 National Semiconductor 54 LS138/DM 54LS138/DM 74LS138, 54 LS139/DM 54LS139/DM 74LS139 Decoders/Demultiplexers General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing appli­


    OCR Scan     		PDF LS138-LS139 LS138/DM 54LS138/DM 74LS138, LS139/DM 54LS139/DM 74LS139 LS138 LS139 LS138-LS139 DM74LS139N

    l381

    Abstract: and gate 74LS138 74ls138 function 74LS138 pin for 74LS138 74LS138 pin diagram SP74SC138F SP74SC138N pin diagram demultiplexer 74LS138
    Text: y SP74SC138 DECODER/DEMULTIPLEXER PIN CONFIGURATION A FEATURES B • Designed for high performance memory decoders in microprocessor systems ■ 3 to 8 line decoders include 3 enable inputs ■ Pin com patible with 74LS138 ■ SPI CMOS technology ■ Full TTL interface capability


    OCR Scan     		PDF SP74SC138 74LS138 SP74SC138 74LS138. 400//A l381 and gate 74LS138 74ls138 function 74LS138 pin for 74LS138 74LS138 pin diagram SP74SC138F SP74SC138N pin diagram demultiplexer 74LS138

    74HCT138N

    Abstract: No abstract text available
    Text: A I R C H I L D Revised February 1999 S E M I C D N D U C T D R tm MM74HCT138 3-to-8 Line Decoder General Description the 74LS138. All inputs are protected from dam age due to static discharge by diodes to V c c and ground. The M M 74H C T138 deco d e r utilizes advanced silicon-gate


    OCR Scan     		PDF MM74HCT138 74HCT138N

    Untitled

    Abstract: No abstract text available
    Text: s e m i c o n d u c t o r Revised February 1999 MM74HCT138 3-to-8 Line Decoder the 74LS138. All inputs are protected from damage due to static discharge by diodes to Vc c and ground. General Description The MM74HCT138 decoder utilizes advanced silicon-gate


    OCR Scan     		PDF MM74HCT138 74LS138. MM74HCT138 MM74HCT

    Ic 74hc138 logic diagram

    Abstract: No abstract text available
    Text: Revised February 1999 S E M IC Q N D U C T O R T M MM74HC138 3-to-8 Line Decoder The decoder’s outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally and pin equiva­ lent to the 74LS138. All inputs are protected from damage due to static discharge by diodes to V qq and ground.


    OCR Scan     		PDF MM74HC138 74LS138. MM74HC138 Ic 74hc138 logic diagram

    74191, 74192, 74193 circuit diagram

    Abstract: IC 7402, 7404, 7408, 7432, 7400 Truth Table 74161 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions counter 74168 74191, 74192, 74193 truth table of ic 7495 A schematic diagram for the IC of 7411
    Text: P L S -W S /H P MAX+PLUS II Programmable Logic Software for HP/Apollo Workstations Data Sheet September 1991, ver. 3 Features □ □ LI LI □ □ □ □ General Description Software support for Classic, M A X 5000, M A X 7000, and ST G E P L D s Runs on H ew lett Packard /A p o llo Series 3000, 3500, 4000, 4500, and


    OCR Scan     		PDF HP400 QIC-24, 60-Mbytetape 74191, 74192, 74193 circuit diagram IC 7402, 7404, 7408, 7432, 7400 Truth Table 74161 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions counter 74168 74191, 74192, 74193 truth table of ic 7495 A schematic diagram for the IC of 7411