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    CY7C1413JV18 Price and Stock

    Infineon Technologies AG CY7C1413JV18-300BZC

    IC SRAM 36MBIT PARALLEL 165FBGA
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    DigiKey CY7C1413JV18-300BZC Tray
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    Infineon Technologies AG CY7C1413JV18-250BZI

    IC SRAM 36MBIT PAR 165FBGA
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    DigiKey CY7C1413JV18-250BZI Tray
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    Rochester Electronics LLC CY7C1413JV18-250BZI

    IC SRAM 36MBIT PAR 165FBGA
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    DigiKey CY7C1413JV18-250BZI Tray 6
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    Rochester Electronics LLC CY7C1413JV18-300BZXC

    IC SRAM 36MBIT PARALLEL 165FBGA
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    DigiKey CY7C1413JV18-300BZXC Tray 5
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    Infineon Technologies AG CY7C1413JV18-300BZXC

    IC SRAM 36MBIT PARALLEL 165FBGA
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    DigiKey CY7C1413JV18-300BZXC Tray
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    CY7C1413JV18 Datasheets (6)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1413JV18 Cypress Semiconductor 36-Mbit QDR-II SRAM 4-Word Burst Architecture Original PDF
    CY7C1413JV18-200BZXI Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 200MHZ 165FBGA Original PDF
    CY7C1413JV18-250BZI Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 250MHZ 165FBGA Original PDF
    CY7C1413JV18-250BZXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 250MHZ 165FBGA Original PDF
    CY7C1413JV18-300BZC Cypress Semiconductor 36-Mbit QDR -II SRAM 4-Word Burst Architecture Original PDF
    CY7C1413JV18-300BZXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 300MHZ 165FBGA Original PDF

    CY7C1413JV18 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: CY7C1413JV18 CY7C1415JV18 36-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1413JV18 – 2M x 18 ■ 300-MHz clock for high bandwidth ■ 4-word burst for reducing address bus frequency


    Original     		PDF CY7C1413JV18 CY7C1415JV18 36-Mbit CY7C1413JV18 300-MHz

    Untitled

    Abstract: No abstract text available
    Text: THIS SPEC IS OBSOLETE Spec No: 001-12557 Spec Title: CY7C1413JV18/CY7C1415JV18, 36-MBIT QDR R II SRAM 4-WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar (NJY) Replaced by: NONE CY7C1413JV18 CY7C1415JV18 36-Mbit QDR II SRAM 4-Word Burst Architecture


    Original     		PDF CY7C1413JV18/CY7C1415JV18, 36-MBIT CY7C1413JV18 CY7C1415JV18 300-MHz

    CY7C1413JV18-300BZXC

    Abstract: CY7C1415JV18-300BZXC CY7C1411JV18 CY7C1413JV18 CY7C1415JV18 CY7C1426JV18
    Text: CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1411JV18 – 4M x 8 ■ 300 MHz clock for high bandwidth


    Original     		PDF CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 36-Mbit CY7C1411JV18 CY7C1413JV18 CY7C1413JV18-300BZXC CY7C1415JV18-300BZXC CY7C1411JV18 CY7C1413JV18 CY7C1415JV18 CY7C1426JV18

    CY7C1411JV18

    Abstract: CY7C1413JV18 CY7C1415JV18 CY7C1426JV18
    Text: CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■


    Original     		PDF CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18 36-Mbit CY7C1411JV18 CY7C1413JV18 CY7C1411JV18 CY7C1413JV18 CY7C1415JV18 CY7C1426JV18