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    ADC VHDL Search Results

    ADC VHDL Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    ADC1038CIWM Rochester Electronics LLC ADC, Successive Approximation, 10-Bit, 1 Func, 8 Channel, Serial Access, PDSO20, SOP-20 Visit Rochester Electronics LLC Buy
    TL505CN Rochester Electronics LLC ADC, Dual-Slope, 10-Bit, 1 Func, 1 Channel, Serial Access, BIMOS, PDIP14, PACKAGE-14 Visit Rochester Electronics LLC Buy
    ML2258CIQ Rochester Electronics LLC ADC, Successive Approximation, 8-Bit, 1 Func, 8 Channel, Parallel, 8 Bits Access, PQCC28, PLASTIC, LCC-28 Visit Rochester Electronics LLC Buy
    CA3310AM Rochester Electronics LLC ADC, Successive Approximation, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PDSO24, PLASTIC, MS-013AD, SOIC-24 Visit Rochester Electronics LLC Buy
    CA3310M Rochester Electronics LLC ADC, Successive Approximation, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PDSO24, PLASTIC, MS-013AD, SOIC-24 Visit Rochester Electronics LLC Buy

    ADC VHDL Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    bit 3252a

    Abstract: No abstract text available
    Text: Quick Q k starrt ADC C1415 5S, ADC1 A 215S S, ADC C1115S, ADC1 A 015S S serie es Demonstra D ation boarrd for ADC C1415S, ADC1215S A S, ADC1115S, ADC1015S A S series Rev. R 5 — Jan nuary 2011 Quick k start Docum ment informattion Info Content Keyw words


    Original     		PDF C1415 ADC1215S C1115S, ADC1015S C1415S, ADC1115S, PCB2001-2, ADC1415S, bit 3252a

    PR68A

    Abstract: QSH-060-01-F-D-A verilog code to generate sine wave PR69A verilog code for sine wave using FPGA 12-bit ADC interface vhdl code for FPGA vhdl code to generate sine wave PR63A sine wave output for fpga using verilog code ADS644X
    Text: Lattice TI ADC Demo User’s Guide January 2008 UG04_01.0 Lattice Semiconductor Lattice TI ADC Demo User’s Guide Introduction This design demonstrates the ability of the LatticeECP2 FPGA to interface to the Texas Instruments TI ADS644X and ADS642X family of ADC ICs using the TI ADS6XXX-EVM (e.g. ADS6245EVM), LatticeECP2


    Original     		PDF ADS644X ADS642X ADS6245EVM) ADS6000 b0110 b0000 b0000000000 PR68A QSH-060-01-F-D-A verilog code to generate sine wave PR69A verilog code for sine wave using FPGA 12-bit ADC interface vhdl code for FPGA vhdl code to generate sine wave PR63A sine wave output for fpga using verilog code

    uart vhdl

    Abstract: XC5VLX50-FF676
    Text: LogiCORE IP XPS SYSMON ADC v3.00.b DS620 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The Xilinx Platform Studio (XPS) System Monitor (SYSMON) Analog-to-Digital Converter (ADC) Intellectual Property (IP) core is a 32-bit slave


    Original     		PDF DS620 32-bit uart vhdl XC5VLX50-FF676

    adc controller vhdl code

    Abstract: vhdl code for time division multiplexer serial analog to digital converter vhdl code vhdl code for parallel to serial converter vhdl code for digital clock output on CPLD XAPP355 adc vhdl source code handspring adc vhdl vhdl program for parallel to serial converter
    Text: Application Note: CoolRunner CPLD R XAPP355 v1.1 January 3, 2002 Summary Serial ADC Interface Using a CoolRunner CPLD This document describes the design implementation for controlling a Texas Instruments ADS7870 Analog to Digital Converter (ADC) in a Xilinx CoolRunner XPLA3™ CPLD.


    Original     		PDF XAPP355 ADS7870 XAPP355 adc controller vhdl code vhdl code for time division multiplexer serial analog to digital converter vhdl code vhdl code for parallel to serial converter vhdl code for digital clock output on CPLD adc vhdl source code handspring adc vhdl vhdl program for parallel to serial converter

    analog to digital converter vhdl coding

    Abstract: XAPP355 vhdl code for time division multiplexer adc controller vhdl code vhdl code for parallel to serial converter adc controller vhdl code download handspring vhdl coding for analog to digital converter serial analog to digital converter vhdl code vhdl code 16 bit processor
    Text: Application Note: CoolRunner CPLD R XAPP355 v1.0 April 30, 2001 Serial ADC Interface Using a CoolRunner CPLD Summary This document describes the design implementation for controlling a Texas Instruments ADS7870 Analog to Digital Converter (ADC) in a Xilinx CoolRunner XPLA3™ CPLD.


    Original     		PDF XAPP355 ADS7870 analog to digital converter vhdl coding XAPP355 vhdl code for time division multiplexer adc controller vhdl code vhdl code for parallel to serial converter adc controller vhdl code download handspring vhdl coding for analog to digital converter serial analog to digital converter vhdl code vhdl code 16 bit processor

    vhdl coding for analog to digital converter

    Abstract: vlsi design physical verification AD8138 AD8351 CL013G N-7075 vhdl coding pipeline adc digital error correction simple ADC Verilog code digital mixer verilog code
    Text: PRODUCT SPECIFICATION nAD10120x2-13m Dual 10-bit 120 MSPS Analog-to-Digital Converter IP FEATURES • • • • • OPM[1:0] CLK EXTREF INP0 • • • • PIPELINE ADC VCM0 INN0 REFP REFN VOLTAGE REFERENCE VCM1 PIPELINE ADC INN1 Communication Receive Channel


    Original     		PDF nAD10120x2-13m 10-bit nAD10120x2-13m N-7075 vhdl coding for analog to digital converter vlsi design physical verification AD8138 AD8351 CL013G vhdl coding pipeline adc digital error correction simple ADC Verilog code digital mixer verilog code

    LSI LOGIC

    Abstract: CW901101 8991K
    Text: CW901101 10-Bit Pipelined ADC Core Overview The CW901101 is a high-performance 10-bit 45MSPS analog-to-digital converter ADC core targeted for digital receivers of cable modems, digital set-top boxes or digital TVs (DTV). The core is compatible with LSI Logic’s FlexStream


    Original     		PDF CW901101 10-Bit 45MSPS B20024 LSI LOGIC 8991K

    TSMC 0.18 um CMOS

    Abstract: verilog code for adc verilog code pipeline square root vhdl coding for analog to digital converter AD8138 AD8351 N-7075 0.18-um CMOS technology characteristics vhdl coding for pipeline TSMC Flash IP
    Text: PRELIMINARY PRODUCT SPECIFICATION nAD10110x2-18a Dual 10-bit 110 MSPS Analog-to-Digital Converter IP FEATURES • • • • • OPM[1:0] CLK EXTREF INP0 • • • • PIPELINE ADC VCM0 INN0 REFP REFN VOLTAGE REFERENCE VCM1 PIPELINE ADC INN1 Communication Receive Channel


    Original     		PDF nAD10110x2-18a 10-bit nAD10110x2-18a N-7075 TSMC 0.18 um CMOS verilog code for adc verilog code pipeline square root vhdl coding for analog to digital converter AD8138 AD8351 0.18-um CMOS technology characteristics vhdl coding for pipeline TSMC Flash IP

    vhdl coding for analog to digital converter

    Abstract: analog to digital converter vhdl coding TSMC 0.18 um CMOS digital to analog converter vhdl coding AD8138 AD8351 N-7075 verilog code pipeline square root vlsi design physical verification vhdl code for digital to analog converter
    Text: PRELIMINARY PRODUCT SPECIFICATION nAD10120x2-13a Dual 10-bit 120 MSPS Analog-to-Digital Converter IP FEATURES • • • • • OPM[1:0] CLK EXTREF INP0 • • • • PIPELINE ADC VCM0 INN0 REFP REFN VOLTAGE REFERENCE VCM1 PIPELINE ADC INN1 Communication Receive Channel


    Original     		PDF nAD10120x2-13a 10-bit nAD10120x2-13a N-7075 vhdl coding for analog to digital converter analog to digital converter vhdl coding TSMC 0.18 um CMOS digital to analog converter vhdl coding AD8138 AD8351 verilog code pipeline square root vlsi design physical verification vhdl code for digital to analog converter

    VHDL code for ADC and DAC SPI with FPGA spartan 3

    Abstract: VHDL code for ADC and DAC SPI with FPGA 12-bit ADC interface vhdl code for FPGA direct sequence spread spectrum virtex JESD204 XAPP876 Xilinx ml507 prbs jesd VHDL code for high speed ADCs using SPI with FPGA virtex 4 date code for ADC
    Text: Application Note: Virtex-5 Family Virtex-5 FPGA Interface to a JESD204A Compliant ADC XAPP876 v1.0.1 February 22, 2010 Author: Marc Defossez Summary This application note describes how to interface the Virtex -5 LXT, SXT, TXT, and FXT devices featuring GTP/GTX transceivers to an analog-to-digital (ADC) converter compliant to JEDEC


    Original     		PDF JESD204A XAPP876 JESD204A) JESD204 JESD204A VHDL code for ADC and DAC SPI with FPGA spartan 3 VHDL code for ADC and DAC SPI with FPGA 12-bit ADC interface vhdl code for FPGA direct sequence spread spectrum virtex XAPP876 Xilinx ml507 prbs jesd VHDL code for high speed ADCs using SPI with FPGA virtex 4 date code for ADC

    VHDL code for ADC and DAC SPI with FPGA

    Abstract: VHDL code for ADC and DAC SPI with FPGA spartan 3 XAPP876 vhdl code for parallel to serial converter 12-bit ADC interface vhdl code for FPGA picoblaze UG347 DS202 JESD204 JESD204A
    Text: Application Note: Virtex-5 Family Virtex-5 FPGA Interface to a JESD204A Compliant ADC XAPP876 v1.0 September 18, 2009 Author: Marc Defossez Summary This application note describes how to interface the Virtex -5 LXT, SXT, TXT, and FXT devices featuring GTP/GTX transceivers to an analog-to-digital (ADC) converter compliant to JEDEC


    Original     		PDF JESD204A XAPP876 JESD204A) JESD204 JESD204A VHDL code for ADC and DAC SPI with FPGA VHDL code for ADC and DAC SPI with FPGA spartan 3 XAPP876 vhdl code for parallel to serial converter 12-bit ADC interface vhdl code for FPGA picoblaze UG347 DS202

    PCB2004-1

    Abstract: No abstract text available
    Text: Quick start ADC1412D, ADC1212D, ADC1112D series Demonstration board for ADC1412D, ADC1212D, ADC1112D series Rev. 10 — 17 December 2010 Quick start Document information Info Content Keywords PCB2004-1, Demonstration board, ADC, Converter, ADC1412D, ADC1212D and ADC1112D series.


    Original     		PDF ADC1412D, ADC1212D, ADC1112D ADC1112D PCB2004-1, ADC1212D PCB2004-1

    Untitled

    Abstract: No abstract text available
    Text: Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series F1 or F2 versions Demonstration board for ADC1415S, A ADC1215S, DC1215S, ADC1115S, ADC1015S series Rev. 5 — January 2011 Quick start Document information Info Content Keywords PCB2122-2, Demonstration board, ADC, Converter


    Original     		PDF ADC1415S, ADC1215S, ADC1115S, ADC1015S PCB2122-2,

    I2S bridge

    Abstract: AN2682 EPM3064 spi to i2s I2S serial bus protocol vhdl code for spi controller implementation on MAX3000A PWM code using vhdl STM32 TIM1 DMA STR711
    Text: AN2682 Application note Connecting I2S audio devices to the STR7/STR9 MCU Introduction This application note describes how to interface the STR7xx SPI peripheral with an audio device Codec, ADC, DAC, filter. using the I2S protocol via an external interface consisting


    Original     		PDF AN2682 STR91x I2S bridge AN2682 EPM3064 spi to i2s I2S serial bus protocol vhdl code for spi controller implementation on MAX3000A PWM code using vhdl STM32 TIM1 DMA STR711

    Untitled

    Abstract: No abstract text available
    Text: Quick start ADC1610S series F1 or F2 versions Demonstration board for ADC1610S series Rev. 5 — January 2011 Quick start Document information Info Content Keywords PCB2131-1, Demonstration board, ADC, Converter Abstract This document describes how to use the demonstration board for the


    Original     		PDF ADC1610S PCB2131-1, ADC1610Sseries.

    AC236

    Abstract: stapl AES-128 wireless encrypt
    Text: Application Note AC236 Fusion FlashROM Introduction The Actel Fusion family, based on the highly successful ProASIC3 Flash FPGA architecture, has been designed as a high-performance, programmable, mixed-signal platform. Fusion supports many peripherals, including embedded Flash memory, Analog-to-Digital Converter ADC , high-drive outputs,


    Original     		PDF AC236 AC236 stapl AES-128 wireless encrypt

    verilog code pipeline square root

    Abstract: AD8138 AD8351 N-7075 tsmc cmos 0.13 um tsmc cmos 0.13 um ADC vhdl coding pipeline adc digital error correction TSMC Flash IP
    Text: PRELIMINARY PRODUCT SPECIFICATION nAD10120-13a 10-bit 120 MSPS Analog-to-Digital Converter IP FEATURES • • • • • • 10-bit ADC Up to 120 MSPS Conversion Rate Single 1.2 V Power Supply 1.0 V p-p Differential Input Excellent Dynamic Performance 59 dBFS SNR at FIN = 10 MHz


    Original     		PDF nAD10120-13a 10-bit nAD10120-13a N-7075 verilog code pipeline square root AD8138 AD8351 tsmc cmos 0.13 um tsmc cmos 0.13 um ADC vhdl coding pipeline adc digital error correction TSMC Flash IP

    TSMC 0.18 um CMOS

    Abstract: vhdl coding for analog to digital converter adc vhdl cmos tsmc 0.18 0.18-um CMOS technology characteristics TSMC 0.18 um CMOS silicon AD8138 AD8351 N-7075 vlsi design physical verification
    Text: PRELIMINARY PRODUCT SPECIFICATION nAD12110-18a 12-bit 110 MSPS Analog-to-Digital Converter IP FEATURES • • • • • • 12-bit ADC Up to 110 MSPS Conversion Rate Single 1.8 V Power Supply 1.5 V p-p Differential Input Excellent Dynamic Performance 67 dBc SNR at FIN = 10 MHz


    Original     		PDF nAD12110-18a 12-bit nAD12110-18a N-7075 TSMC 0.18 um CMOS vhdl coding for analog to digital converter adc vhdl cmos tsmc 0.18 0.18-um CMOS technology characteristics TSMC 0.18 um CMOS silicon AD8138 AD8351 vlsi design physical verification

    TSMC 0.18 um CMOS

    Abstract: 0.18-um CMOS technology characteristics tsmc 0.18 flash tsmc cmos 0.18 um AD8138 AD8351 N-7075 vhdl coding for analog to digital converter verilog code for adc verilog code of analog mixed mode
    Text: PRELIMINARY PRODUCT SPECIFICATION nAD10110-18a 10-bit 110 MSPS Analog-to-Digital Converter IP FEATURES • • • • • • 10-bit ADC Up to 110 MSPS Conversion Rate Single 1.8 V Power Supply 1.5 V p-p Differential Input Excellent Dynamic Performance 59 dBFS SNR at FIN = 10 MHz


    Original     		PDF nAD10110-18a 10-bit nAD10110-18a N-7075 TSMC 0.18 um CMOS 0.18-um CMOS technology characteristics tsmc 0.18 flash tsmc cmos 0.18 um AD8138 AD8351 vhdl coding for analog to digital converter verilog code for adc verilog code of analog mixed mode

    12-bit ADC interface vhdl code for FPGA

    Abstract: iodelay ISERDES XC5VLX50T-FF1136.xls VHDL code for high speed ADCs using SPI with FPGA 12-bit ADC interface vhdl complete code for FPGA virtex 4 date code for ADC XAPP866 iodelay for adc parallel data and fpga interface UCF virtex-4
    Text: Application Note: Virtex-4 and Virtex-5 FPGAs R XAPP866 v3.0 April 7, 2008 An Interface for Texas Instruments Analog-to-Digital Converters with Serial LVDS Outputs Author: Marc Defossez Summary This application note describes how to interface a Texas Instruments analog-to-digital


    Original     		PDF XAPP866 12-bit ADC interface vhdl code for FPGA iodelay ISERDES XC5VLX50T-FF1136.xls VHDL code for high speed ADCs using SPI with FPGA 12-bit ADC interface vhdl complete code for FPGA virtex 4 date code for ADC XAPP866 iodelay for adc parallel data and fpga interface UCF virtex-4

    Untitled

    Abstract: No abstract text available
    Text: ADS528x EVM User's Guide User's Guide January 2008 SLAU205 2 SLAU205 – January 2008 Submit Documentation Feedback Contents 1 2 3 4 Overview . 5


    Original     		PDF ADS528x SLAU205

    verilog code for adc

    Abstract: adc controller vhdl code adc vhdl A2F500 adc verilog adc vhdl source code verilog code for apb PDMA verilog code for ahb bus matrix H190
    Text: Application Note AC352 SmartFusion: Using ACE with PDMA Table of Contents Introduction . . . . . . . . Design Example Overview Running the Design . . . . Conclusion . . . . . . . . Appendix A - Design Files . . . . . . . . . . . . . . . . . . . . . . . . .


    Original     		PDF AC352 verilog code for adc adc controller vhdl code adc vhdl A2F500 adc verilog adc vhdl source code verilog code for apb PDMA verilog code for ahb bus matrix H190

    verilog code voltage regulator

    Abstract: CORE8051 scaler verilog code verilog code for apb ADC rtl code vhdl code for 16 BIT BINARY DIVIDER microcontroller using vhdl verilog code for adc adc vhdl verilog code for four bit binary divider
    Text: CoreAI Product Summary Synthesis and Simulation Support Intended Use • Analog Interface Control Using a Microprocessor/ Microcontroller and an Actel FusionTM Device • Voltage, Current, and Temperature Monitoring Using a Microprocessor/Microcontroller and an


    Original     		PDF 16-Bit verilog code voltage regulator CORE8051 scaler verilog code verilog code for apb ADC rtl code vhdl code for 16 BIT BINARY DIVIDER microcontroller using vhdl verilog code for adc adc vhdl verilog code for four bit binary divider

    GMLAN

    Abstract: bitron GSM based home appliance control system BOSCH wiper motor 2X16 lcd vhdl borg lcd valeo lcd 2X16 hitachi schneider lcd TV Purcell
    Text: HERE & NOW AVAILABLE & POWERFUL MICRO SOLUTIONS Market Position Embedded Flash Products Status Support Tools Key Applications Top 10 Worldwide 8 bit MCUs Millions of $US (Dataquest 5/99) 1998 Rank 1998 Revenue 98 Market Share(%) 1,362 24.1 1 Motorola


    Original     		PDF 100Mu ST62/72 ST92141 ST1OF167 GMLAN bitron GSM based home appliance control system BOSCH wiper motor 2X16 lcd vhdl borg lcd valeo lcd 2X16 hitachi schneider lcd TV Purcell